Re: Segmentation fault when compiling GCC with new RTL pass

[Tomasz Jankowski <tomcioj at gmail dot com>]

Hello,

2012/10/3 Ian Lance Taylor <iant@google.com>:
>
> I don't know what rto:SI means and I don't know what you are trying to
> do.  If I were trying to insert an insn at a particular point I would
> not define a new RTL code, I would use UNSPEC_VOLATILE.
>

Ok, now I see it was my fault and I was emitting new "rto" instruction
in wrong place.

I have last feature to implement in machine description and RTL pass -
SIMD instruction. As I see implementing SIMDs in GCC is a bit odd and
there's no example. Anyway, I have to implement add instruction called
"radd". As I know SIMD instructions usually operates on operands
packed in registers (like on x86, where we have 128 bit registers for
MMX/SSE). "radd" instructions operates of operands stored in two sets
of registers, were I we have one operand per registers. For me it's
completely new approach and I don't know how to deal with it... What's
more we specify only first set of registers in instruction call,
second registers set is based on first on. Example, when we write:

    radd rD1, rA1, rB1

will result in performing:

   rD1 = rA1 + rB1
   rD2 = rA2 + rB2

Processor implicitly knows where to look for second set of registers
(rD2, rA2, rB2), because there is strong relation between rD1 and rD2:
rD2 is exactly after rD1 (the same apply to [rA1,rA2] and [rB1,rB2]).
Example pseudo asm code showing how it we should use this instruction:

   mov 10, r5
   mov 10, r6
   mov 2, r10
   mov 3, r11
   radd r0, r5, r10

Code above will perform such calculation:

    r0 = r5 + r10
    r1 = r6 + r11

Now I really stuck, I don't know how to deal with vectorization and
how to handle register allocation for this "radd" (if I have to do
that....).