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Re: "rep ret" even for Intel CPUs?
kevin diggs <firstname.lastname@example.org> writes:
> Uh ... "rep; ret"? Where do I look to see what this is?
Some AMD processors have a one cycle pipeline stall when a "ret"
instruction is the target of a conditional jump or is immediately
preceded by a conditional jump. To avoid this, gcc generates "rep; ret"
in those cases intead. Since the "rep" prefix means nothing with the
"ret" instruction, this effectively becomes a two byte "ret"
instruction, and that is sufficient to avoid the pipeline bubble.