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Re: ARM Configure Targets
- From: Remy Fenn <rem at riscnx dot net>
- To: "gcc-help at gcc dot gnu dot org" <gcc-help at gcc dot gnu dot org>
- Date: Thu, 06 Dec 2007 04:31:50 +0000
- Subject: Re: ARM Configure Targets
- References: <47574DD1.9000808@duaneellis.com>
On Thu, 2007-12-06 at 01:18, Duane Ellis wrote:
> Remy> Where can I find further information on specific [ARM] targets?
> You should learn about the "cross-gcc" mailing list.
>
> See this site for the archive: http://sourceware.org/ml/crossgcc/
>
> What is the _exact_ target (chip) you want?
> ie: A full arm-soc solution (like Xscale)
> or: A tiny arm7tdmi micro-controller type, with only 32K flash on
> chip?
>
> What is the _exact_ OS the board will run?
> ie: Roll your own
> or: Linux, great for Xscale, won't run on tiny micro-controllers.
> or: Some commercial thing, there are many.
> or: Something totally weirdo..
>
> Depending upon your answer, I might have something that will help you.
>
> -Duane.
I'm currently using a gcc configured for arm-elf which works fine for
cross-compiling Xscale software to run on embedded Debian.
I have raised this issue initially because I was unable to find an
official list of the specific configure targets which are available to
me when configuring gcc as a cross-compiler in this case for Arm/Linux
(purely out of curiousity). My particular problem is in understanding
why I should use arm-elf (which seems to be the defacto for a variety of
situations) rather than arm-linux or arm-linux-elf or arm-elf-linux or
whatever other combinations are currently available.
What are the supported configure targets, why does <blank> specific
target exist, how exactly does it differ from its relatives (e.g
arm-elf, arm-linux) and what benefits does it offer? These are questions
which have been burning inside me for a while now and I would be very
pleased if they could be answered if nothing else than for the sake of
my own sanity.
I'll go familiarise myself with crossgcc and see what I can come up
with.
Thanks.
--
Remy Fenn Email: rem@riscnx.net
Dept. Systems Engineering
Medway School of Engineering
The University of Greenwich
United Kingdom