question aboue ARM code generation?

["阎淼" <yanmiaobest at gmail dot com>]

Hi

   I am build vxWorks for ARM 920t, using gcc 3.4.4 which I think is
slightly modified by WindRiver, it accepts the -t5 and -t4 options
which I don't find in the gcc user manual. Code generation with -t5
option and without -t5 option is different. here is my test code:

void AT91USIntRx(AT91_US_CHAN *pChan)
{
	char inChar;
	inChar = pChan->regs->dbgu_rhr;
	inChar = dbgu->dbgu_rhr;
	putc(inChar);
	(*pChan->putRcvChar)(pChan->putRcvArg, inChar);
}

objdump results( complied with -t5 option):

(*pChan->putRcvChar)(pChan->putRcvArg, inChar);

20005ca0:	e51b3010 	ldr	r3, [fp, #-16]
20005ca4:	e51b2010 	ldr	r2, [fp, #-16]
20005ca8:	e55b1011 	ldrb	r1, [fp, #-17]
20005cac:	e5933008 	ldr	r3, [r3, #8]
20005cb0:	e5920010 	ldr	r0, [r2, #16]
20005cb4:	e12fff33 	blx	r3


when executing the blx instruction, the application is out of control!

objdump results( complied without -t5 option):

(*pChan->putRcvChar)(pChan->putRcvArg, inChar);

20005ca8:	e51b3010 	ldr	r3, [fp, #-16]
20005cac:	e51b2010 	ldr	r2, [fp, #-16]
20005cb0:	e55b1011 	ldrb	r1, [fp, #-17]
20005cb4:	e5933008 	ldr	r3, [r3, #8]
20005cb8:	e5920010 	ldr	r0, [r2, #16]
20005cbc:	e1a0e00f 	mov	lr, pc
20005cc0:	e1a0f003 	mov	pc, r3

this version works very well. It seems the 'blx' causes CPU into thumb
state which vxWorks does not support. why this happen? blx can not be
used in ARM instructions?

Maybe it is not proper to send this email here, but I really need help.