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Porting gcc to new core
- From: Balaji S <sivanbalaji at acmet dot com>
- To: gcc-help at gcc dot gnu dot org
- Date: Thu, 20 May 2004 13:20:51 +0530
- Subject: Porting gcc to new core
- Organization: Acme Technologies Pvt. Ltd.
I am working on porting gcc to a core with the following characteristics:
1. Orthogonal and irregular (as ix86) byte register set
2. Pipelined RISC with blocking loads and no delay slots
3. Can load/store byte/half word/word/double word memory into register(s)
4. Segmented memory
does anybody know/guide/point the reference architecture already ported with similar characteristics.
thanks in advance.