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r254092 - in /trunk/gcc: ChangeLog config/riscv...
- From: palmer at gcc dot gnu dot org
- To: gcc-cvs at gcc dot gnu dot org
- Date: Wed, 25 Oct 2017 22:45:55 -0000
- Subject: r254092 - in /trunk/gcc: ChangeLog config/riscv...
Author: palmer
Date: Wed Oct 25 22:45:55 2017
New Revision: 254092
URL: https://gcc.gnu.org/viewcvs?rev=254092&root=gcc&view=rev
Log:
RISC-V: Add Sign/Zero extend patterns for PIC loads
Loads on RISC-V are sign-extending by default, but we weren't telling
GCC this in our PIC load patterns. This corrects the problem, and adds
a zero-extending pattern as well.
gcc/ChangeLog
2017-10-25 Palmer Dabbelt <palmer@dabbelt.com>
* config/riscv/riscv.md (ZERO_EXTEND_LOAD): Define.
* config/riscv/pic.md (local_pic_load): Rename to local_pic_load_s,
mark as a sign-extending load.
(local_pic_load_u): Define.
Modified:
trunk/gcc/ChangeLog
trunk/gcc/config/riscv/pic.md
trunk/gcc/config/riscv/riscv.md