r242277 - in /branches/ARM/sve-branch/gcc: doc/...

[rsandifo at gcc dot gnu dot org]

Author: rsandifo
Date: Fri Nov 11 17:32:34 2016
New Revision: 242277

URL: https://gcc.gnu.org/viewcvs?rev=242277&root=gcc&view=rev
Log:
Base subreg rules on REGMODE_NATURAL_SIZE rather than UNITS_PER_WORD

Originally subregs operated at the word level and subreg offsets
were measured in words.  The offset units were later changed from
words to bytes (SUBREG_WORD became SUBREG_BYTE), but the fundamental
assumption that subregs should operate at the word level remained.
Whether (subreg:M1 (reg:M2 R2) N) is well-formed depended on the
way that M1 and M2 partitioned into words and whether the subword
part of N represented a lowpart.  However, some questions depended
instead on the macro REGMODE_NATURAL_SIZE, which was introduced
as part of the patch that moved from SUBREG_WORD to SUBREG_BYTE.
It is used to decide whether setting (subreg:M1 (reg:M2 R2) N)
clobbers all of R2 or just part of it (df_read_modify_subreg).

Using words doesn't really make sense for modern vector
architectures.  Vector registers are usually bigger than
a word and:

(a) setting the scalar lowpart of them usually clobbers the
    rest of the register (contrary to the subreg rules,
    where only the containing words should be clobbered).

(b) high words of vector registers are often not independently
    addressable, even though that's what the subreg rules expect.

This patch therefore uses REGMODE_NATURAL_SIZE instead of
UNITS_PER_WORD to determine the size of the independently
addressable blocks in an inner register.

This is needed for SVE because the number of words in a vector
mode isn't known at compile time, so isn't a sensible basis
for calculating the number of registers.

The only existing port to define REGMODE_NATURAL_SIZE is
64-bit SPARC, where FP registers are 32 bits.  (This is the
opposite of the use case for SVE, since the natural division
is smaller than a word.)  I compiled the testsuite before and
after the patch for sparc64-linux-gnu and the only test whose
assembly changed was g++.dg/debug/pr65678.C, where the order
of two independent stores was reversed and where a different
register was picked for one pseudo.  The new code was
otherwise equivalent to the old code.

Modified:
    branches/ARM/sve-branch/gcc/doc/rtl.texi
    branches/ARM/sve-branch/gcc/emit-rtl.c
    branches/ARM/sve-branch/gcc/expr.c