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r212698 - in /branches/linaro/gcc-4_9-branch/gc...

From: yroux at gcc dot gnu dot org
To: gcc-cvs at gcc dot gnu dot org
Date: Wed, 16 Jul 2014 21:51:49 -0000
Subject: r212698 - in /branches/linaro/gcc-4_9-branch/gc...
Author: yroux
Date: Wed Jul 16 21:51:49 2014
New Revision: 212698

URL: https://gcc.gnu.org/viewcvs?rev=212698&root=gcc&view=rev
Log:
gcc/
2014-07-16  Yvan Roux  <yvan.roux@linaro.org>

	Backport from trunk r210151.
	2014-05-07  Alan Lawrence  <alan.lawrence@arm.com>

	* config/aarch64/arm_neon.h (vtrn1_f32, vtrn1_p8, vtrn1_p16, vtrn1_s8,
	vtrn1_s16, vtrn1_s32, vtrn1_u8, vtrn1_u16, vtrn1_u32, vtrn1q_f32,
	vtrn1q_f64, vtrn1q_p8, vtrn1q_p16, vtrn1q_s8, vtrn1q_s16, vtrn1q_s32,
	vtrn1q_s64, vtrn1q_u8, vtrn1q_u16, vtrn1q_u32, vtrn1q_u64, vtrn2_f32,
	vtrn2_p8, vtrn2_p16, vtrn2_s8, vtrn2_s16, vtrn2_s32, vtrn2_u8,
	vtrn2_u16, vtrn2_u32, vtrn2q_f32, vtrn2q_f64, vtrn2q_p8, vtrn2q_p16,
	vtrn2q_s8, vtrn2q_s16, vtrn2q_s32, vtrn2q_s64, vtrn2q_u8, vtrn2q_u16,
	vtrn2q_u32, vtrn2q_u64): Replace temporary asm with __builtin_shuffle.

gcc/testsuite/
2014-07-16  Yvan Roux  <yvan.roux@linaro.org>

	Backport from trunk r210148, 210151, 210422.
	2014-05-07  Alan Lawrence  <alan.lawrence@arm.com>

	* gcc.target/aarch64/simd/vtrnf32_1.c: New file.
	* gcc.target/aarch64/simd/vtrnf32.x: New file.
	* gcc.target/aarch64/simd/vtrnp16_1.c: New file.
	* gcc.target/aarch64/simd/vtrnp16.x: New file.
	* gcc.target/aarch64/simd/vtrnp8_1.c: New file.
	* gcc.target/aarch64/simd/vtrnp8.x: New file.
	* gcc.target/aarch64/simd/vtrnqf32_1.c: New file.
	* gcc.target/aarch64/simd/vtrnqf32.x: New file.
	* gcc.target/aarch64/simd/vtrnqp16_1.c: New file.
	* gcc.target/aarch64/simd/vtrnqp16.x: New file.
	* gcc.target/aarch64/simd/vtrnqp8_1.c: New file.
	* gcc.target/aarch64/simd/vtrnqp8.x: New file.
	* gcc.target/aarch64/simd/vtrnqs16_1.c: New file.
	* gcc.target/aarch64/simd/vtrnqs16.x: New file.
	* gcc.target/aarch64/simd/vtrnqs32_1.c: New file.
	* gcc.target/aarch64/simd/vtrnqs32.x: New file.
	* gcc.target/aarch64/simd/vtrnqs8_1.c: New file.
	* gcc.target/aarch64/simd/vtrnqs8.x: New file.
	* gcc.target/aarch64/simd/vtrnqu16_1.c: New file.
	* gcc.target/aarch64/simd/vtrnqu16.x: New file.
	* gcc.target/aarch64/simd/vtrnqu32_1.c: New file.
	* gcc.target/aarch64/simd/vtrnqu32.x: New file.
	* gcc.target/aarch64/simd/vtrnqu8_1.c: New file.
	* gcc.target/aarch64/simd/vtrnqu8.x: New file.
	* gcc.target/aarch64/simd/vtrns16_1.c: New file.
	* gcc.target/aarch64/simd/vtrns16.x: New file.
	* gcc.target/aarch64/simd/vtrns32_1.c: New file.
	* gcc.target/aarch64/simd/vtrns32.x: New file.
	* gcc.target/aarch64/simd/vtrns8_1.c: New file.
	* gcc.target/aarch64/simd/vtrns8.x: New file.
	* gcc.target/aarch64/simd/vtrnu16_1.c: New file.
	* gcc.target/aarch64/simd/vtrnu16.x: New file.
	* gcc.target/aarch64/simd/vtrnu32_1.c: New file.
	* gcc.target/aarch64/simd/vtrnu32.x: New file.
	* gcc.target/aarch64/simd/vtrnu8_1.c: New file.
	* gcc.target/aarch64/simd/vtrnu8.x: New file.

	2014-05-07  Alan Lawrence  <alan.lawrence@arm.com>

	* gcc.target/aarch64/vtrns32.c: Expect zip[12] insn rather than trn[12].
	* gcc.target/aarch64/vtrnu32.c: Likewise.
	* gcc.target/aarch64/vtrnf32.c: Likewise.

	2014-05-14  Alan Lawrence  <alan.lawrence@arm.com>

	* gcc.target/arm/simd/vtrnqf32_1.c: New file.
	* gcc.target/arm/simd/vtrnqp16_1.c: New file.
	* gcc.target/arm/simd/vtrnqp8_1.c: New file.
	* gcc.target/arm/simd/vtrnqs16_1.c: New file.
	* gcc.target/arm/simd/vtrnqs32_1.c: New file.
	* gcc.target/arm/simd/vtrnqs8_1.c: New file.
	* gcc.target/arm/simd/vtrnqu16_1.c: New file.
	* gcc.target/arm/simd/vtrnqu32_1.c: New file.
	* gcc.target/arm/simd/vtrnqu8_1.c: New file.
	* gcc.target/arm/simd/vtrnf32_1.c: New file.
	* gcc.target/arm/simd/vtrnp16_1.c: New file.
	* gcc.target/arm/simd/vtrnp8_1.c: New file.
	* gcc.target/arm/simd/vtrns16_1.c: New file.
	* gcc.target/arm/simd/vtrns32_1.c: New file.
	* gcc.target/arm/simd/vtrns8_1.c: New file.
	* gcc.target/arm/simd/vtrnu16_1.c: New file.
	* gcc.target/arm/simd/vtrnu32_1.c: New file.
	* gcc.target/arm/simd/vtrnu8_1.c: New file.


Added:
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/vtrnf32.x
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/vtrnf32_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/vtrnp16.x
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/vtrnp16_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/vtrnp8.x
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/vtrnp8_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/vtrnqf32.x
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/vtrnqf32_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/vtrnqp16.x
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/vtrnqp16_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/vtrnqp8.x
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/vtrnqp8_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/vtrnqs16.x
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/vtrnqs16_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/vtrnqs32.x
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/vtrnqs32_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/vtrnqs8.x
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/vtrnqs8_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/vtrnqu16.x
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/vtrnqu16_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/vtrnqu32.x
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/vtrnqu32_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/vtrnqu8.x
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/vtrnqu8_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/vtrns16.x
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/vtrns16_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/vtrns32.x
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/vtrns32_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/vtrns8.x
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/vtrns8_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/vtrnu16.x
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/vtrnu16_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/vtrnu32.x
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/vtrnu32_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/vtrnu8.x
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/vtrnu8_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/arm/simd/vtrnf32_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/arm/simd/vtrnp16_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/arm/simd/vtrnp8_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/arm/simd/vtrnqf32_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/arm/simd/vtrnqp16_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/arm/simd/vtrnqp8_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/arm/simd/vtrnqs16_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/arm/simd/vtrnqs32_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/arm/simd/vtrnqs8_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/arm/simd/vtrnqu16_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/arm/simd/vtrnqu32_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/arm/simd/vtrnqu8_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/arm/simd/vtrns16_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/arm/simd/vtrns32_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/arm/simd/vtrns8_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/arm/simd/vtrnu16_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/arm/simd/vtrnu32_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/arm/simd/vtrnu8_1.c
Modified:
    branches/linaro/gcc-4_9-branch/gcc/ChangeLog.linaro
    branches/linaro/gcc-4_9-branch/gcc/config/aarch64/arm_neon.h
    branches/linaro/gcc-4_9-branch/gcc/testsuite/ChangeLog.linaro
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