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r212677 - in /branches/linaro/gcc-4_9-branch/gc...

From: yroux at gcc dot gnu dot org
To: gcc-cvs at gcc dot gnu dot org
Date: Wed, 16 Jul 2014 16:03:58 -0000
Subject: r212677 - in /branches/linaro/gcc-4_9-branch/gc...
Author: yroux
Date: Wed Jul 16 16:03:58 2014
New Revision: 212677

URL: https://gcc.gnu.org/viewcvs?rev=212677&root=gcc&view=rev
Log:
gcc/
2014-07-16  Yvan Roux  <yvan.roux@linaro.org>

	Backport from trunk r211058, 211177.
	2014-05-29  Alan Lawrence  <alan.lawrence@arm.com>

	* config/aarch64/aarch64-builtins.c (aarch64_types_binopv_qualifiers,
	TYPES_BINOPV): New static data.
	* config/aarch64/aarch64-simd-builtins.def (im_lane_bound): New builtin.
	* config/aarch64/aarch64-simd.md (aarch64_ext, aarch64_im_lane_boundsi):
	New patterns.
	* config/aarch64/aarch64.c (aarch64_expand_vec_perm_const_1): Match
	patterns for EXT.
	(aarch64_evpc_ext): New function.

	* config/aarch64/iterators.md (UNSPEC_EXT): New enum element.

	* config/aarch64/arm_neon.h (vext_f32, vext_f64, vext_p8, vext_p16,
	vext_s8, vext_s16, vext_s32, vext_s64, vext_u8, vext_u16, vext_u32,
	vext_u64, vextq_f32, vextq_f64, vextq_p8, vextq_p16, vextq_s8,
	vextq_s16, vextq_s32, vextq_s64, vextq_u8, vextq_u16, vextq_u32,
	vextq_u64): Replace __asm with __builtin_shuffle and im_lane_boundsi.

	2014-06-03  Alan Lawrence  <alan.lawrence@arm.com>

	* config/aarch64/aarch64.c (aarch64_evpc_ext): allow and handle
	location == 0.

gcc/testsuite/
2014-07-16  Yvan Roux  <yvan.roux@linaro.org>

	Backport from trunk r210152, 211059.
	2014-05-29  Alan Lawrence  <alan.lawrence@arm.com>

	* gcc.target/arm/simd/vextQf32_1.c: New file.
	* gcc.target/arm/simd/vextQp16_1.c: New file.
	* gcc.target/arm/simd/vextQp8_1.c: New file.
	* gcc.target/arm/simd/vextQs16_1.c: New file.
	* gcc.target/arm/simd/vextQs32_1.c: New file.
	* gcc.target/arm/simd/vextQs64_1.c: New file.
	* gcc.target/arm/simd/vextQs8_1.c: New file.
	* gcc.target/arm/simd/vextQu16_1.c: New file.
	* gcc.target/arm/simd/vextQu32_1.c: New file.
	* gcc.target/arm/simd/vextQu64_1.c: New file.
	* gcc.target/arm/simd/vextQu8_1.c: New file.
	* gcc.target/arm/simd/vextQp64_1.c: New file.
	* gcc.target/arm/simd/vextf32_1.c: New file.
	* gcc.target/arm/simd/vextp16_1.c: New file.
	* gcc.target/arm/simd/vextp8_1.c: New file.
	* gcc.target/arm/simd/vexts16_1.c: New file.
	* gcc.target/arm/simd/vexts32_1.c: New file.
	* gcc.target/arm/simd/vexts64_1.c: New file.
	* gcc.target/arm/simd/vexts8_1.c: New file.
	* gcc.target/arm/simd/vextu16_1.c: New file.
	* gcc.target/arm/simd/vextu32_1.c: New file.
	* gcc.target/arm/simd/vextu64_1.c: New file.
	* gcc.target/arm/simd/vextu8_1.c: New file.
	* gcc.target/arm/simd/vextp64_1.c: New file.

	2014-05-07  Alan Lawrence  <alan.lawrence@arm.com>

	gcc.target/aarch64/simd/ext_f32.x: New file.
	gcc.target/aarch64/simd/ext_f32_1.c: New file.
	gcc.target/aarch64/simd/ext_p16.x: New file.
	gcc.target/aarch64/simd/ext_p16_1.c: New file.
	gcc.target/aarch64/simd/ext_p8.x: New file.
	gcc.target/aarch64/simd/ext_p8_1.c: New file.
	gcc.target/aarch64/simd/ext_s16.x: New file.
	gcc.target/aarch64/simd/ext_s16_1.c: New file.
	gcc.target/aarch64/simd/ext_s32.x: New file.
	gcc.target/aarch64/simd/ext_s32_1.c: New file.
	gcc.target/aarch64/simd/ext_s64.x: New file.
	gcc.target/aarch64/simd/ext_s64_1.c: New file.
	gcc.target/aarch64/simd/ext_s8.x: New file.
	gcc.target/aarch64/simd/ext_s8_1.c: New file.
	gcc.target/aarch64/simd/ext_u16.x: New file.
	gcc.target/aarch64/simd/ext_u16_1.c: New file.
	gcc.target/aarch64/simd/ext_u32.x: New file.
	gcc.target/aarch64/simd/ext_u32_1.c: New file.
	gcc.target/aarch64/simd/ext_u64.x: New file.
	gcc.target/aarch64/simd/ext_u64_1.c: New file.
	gcc.target/aarch64/simd/ext_u8.x: New file.
	gcc.target/aarch64/simd/ext_u8_1.c: New file.
	gcc.target/aarch64/simd/ext_f64.c: New file.
	gcc.target/aarch64/simd/extq_f32.x: New file.
	gcc.target/aarch64/simd/extq_f32_1.c: New file.
	gcc.target/aarch64/simd/extq_p16.x: New file.
	gcc.target/aarch64/simd/extq_p16_1.c: New file.
	gcc.target/aarch64/simd/extq_p8.x: New file.
	gcc.target/aarch64/simd/extq_p8_1.c: New file.
	gcc.target/aarch64/simd/extq_s16.x: New file.
	gcc.target/aarch64/simd/extq_s16_1.c: New file.
	gcc.target/aarch64/simd/extq_s32.x: New file.
	gcc.target/aarch64/simd/extq_s32_1.c: New file.
	gcc.target/aarch64/simd/extq_s64.x: New file.
	gcc.target/aarch64/simd/extq_s64_1.c: New file.
	gcc.target/aarch64/simd/extq_s8.x: New file.
	gcc.target/aarch64/simd/extq_s8_1.c: New file.
	gcc.target/aarch64/simd/extq_u16.x: New file.
	gcc.target/aarch64/simd/extq_u16_1.c: New file.
	gcc.target/aarch64/simd/extq_u32.x: New file.


Added:
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/ext_f32.x
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/ext_f32_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/ext_f64_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/ext_p16.x
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/ext_p16_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/ext_p8.x
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/ext_p8_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/ext_s16.x
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/ext_s16_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/ext_s32.x
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/ext_s32_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/ext_s64.x
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/ext_s64_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/ext_s8.x
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/ext_s8_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/ext_u16.x
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/ext_u16_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/ext_u32.x
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/ext_u32_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/ext_u64.x
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/ext_u64_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/ext_u8.x
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/ext_u8_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/extq_f32.x
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/extq_f32_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/extq_f64_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/extq_p16.x
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/extq_p16_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/extq_p8.x
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/extq_p8_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/extq_s16.x
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/extq_s16_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/extq_s32.x
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/extq_s32_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/extq_s64.x
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/extq_s64_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/extq_s8.x
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/extq_s8_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/extq_u16.x
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/extq_u16_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/extq_u32.x
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/extq_u32_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/extq_u64.x
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/extq_u64_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/extq_u8.x
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/simd/extq_u8_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/arm/simd/vextQf32_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/arm/simd/vextQp16_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/arm/simd/vextQp64_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/arm/simd/vextQp8_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/arm/simd/vextQs16_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/arm/simd/vextQs32_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/arm/simd/vextQs64_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/arm/simd/vextQs8_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/arm/simd/vextQu16_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/arm/simd/vextQu32_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/arm/simd/vextQu64_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/arm/simd/vextQu8_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/arm/simd/vextf32_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/arm/simd/vextp16_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/arm/simd/vextp64_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/arm/simd/vextp8_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/arm/simd/vexts16_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/arm/simd/vexts32_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/arm/simd/vexts64_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/arm/simd/vexts8_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/arm/simd/vextu16_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/arm/simd/vextu32_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/arm/simd/vextu64_1.c
    branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/arm/simd/vextu8_1.c
Modified:
    branches/linaro/gcc-4_9-branch/gcc/ChangeLog.linaro
    branches/linaro/gcc-4_9-branch/gcc/config/aarch64/aarch64-builtins.c
    branches/linaro/gcc-4_9-branch/gcc/config/aarch64/aarch64-simd-builtins.def
    branches/linaro/gcc-4_9-branch/gcc/config/aarch64/aarch64-simd.md
    branches/linaro/gcc-4_9-branch/gcc/config/aarch64/aarch64.c
    branches/linaro/gcc-4_9-branch/gcc/config/aarch64/arm_neon.h
    branches/linaro/gcc-4_9-branch/gcc/config/aarch64/iterators.md
    branches/linaro/gcc-4_9-branch/gcc/testsuite/ChangeLog.linaro
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