[Bug target/81803] [7/8 regression] miscompilation at -O1 on mips64el

["mpf at gcc dot gnu.org" <gcc-bugzilla at gcc dot gnu dot org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81803

--- Comment #7 from mpf at gcc dot gnu.org ---
(In reply to Eric Botcazou from comment #6)
> > I have just noticed this which seems curious. Is the 39 -> 40 combine really
> > a valid transformation? It seems we've lost the sign extension and we're
> > just putting a 32-bit value into a 64-bit register without trying to clear
> > the upper bits anymore?
> 
> Yes, for WORD_REGISTER_OPERATIONS architectures the combiner can do things
> like that, although there might be bugs lurking of course.

Yes, this looks like a valid transformation to me. The upper 63 bits on r235
are guaranteed to be zero so the sign extension can be eliminated trivially but
also it is actually a zero extension and could be eliminated because the
LOAD_EXTEND_OP is ZERO_EXT for HImode.

Not looking forward to investigating this!