[Bug target/72748] [7 Regression] ICE on valid code at -O2 and -O3 with -g enabled in 64-bit mode on x86_64-linux-gnu: in simplify_subreg, at simplify-rtx.c:5952

["hjl at gcc dot gnu.org" <gcc-bugzilla at gcc dot gnu dot org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=72748

--- Comment #3 from hjl at gcc dot gnu.org <hjl at gcc dot gnu.org> ---
Author: hjl
Date: Mon Aug  1 14:46:01 2016
New Revision: 238956

URL: https://gcc.gnu.org/viewcvs?rev=238956&root=gcc&view=rev
Log:
Convert V1TImode register to TImode in debug insn

TImode register referenced in debug insn can be converted to V1TImode by
scalar to vector optimization.  When converting a TImode store to V1TImode,
we need to check all debug insns on its use chain to convert the V1TImode
register to SUBREG TImode if source register is undefined.

gcc/

        PR target/72748
        * config/i386/i386.c (timode_scalar_chain::convert_insn): Call
        fix_debug_reg_uses after changing source register mode to
        V1TImode if source register is undefined.

gcc/testsuite/

        PR target/72748
        * gcc.target/i386/pr72748.c: New test.

Added:
    trunk/gcc/testsuite/gcc.target/i386/pr72748.c
Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/config/i386/i386.c
    trunk/gcc/testsuite/ChangeLog