[Bug target/66358] [5/6 Regression] [SH] ICE: in extract_constrain_insn, at recog.c:2232

["olegendo at gcc dot gnu.org" <gcc-bugzilla at gcc dot gnu dot org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66358

--- Comment #14 from Oleg Endo <olegendo at gcc dot gnu.org> ---
It seems the problem is adjacent insns that need R0:

(insn 10503 2627 2628 402 (set (reg:SI 2424)
        (sign_extend:SI (mem:QI (plus:SI (reg/v/f:SI 243 [ p2 ])
                    (const_int 2 [0x2])) [0 MEM[(unsigned char *)p2_97 + 2B]+0
S1 A8]))) ../../ORIG/trunk/libiberty/regex.c:7109 232
{*extendqisi2_compact_mem_disp}
     (nil))
(note 2628 10503 10505 402 NOTE_INSN_DELETED)
(insn 10505 2628 2629 402 (set (reg:SI 2425)
        (sign_extend:SI (mem:QI (plus:SI (reg/f:SI 774 [ D.8751 ])
                    (const_int 5 [0x5])) [0 MEM[(unsigned char *)_1000 + 5B]+0
S1 A8]))) ../../ORIG/trunk/libiberty/regex.c:7109 232
{*extendqisi2_compact_mem_disp}
     (nil))
(note 2629 10505 2631 402 NOTE_INSN_DELETED)
(note 2631 2629 10507 402 NOTE_INSN_DELETED)
(insn 10507 2631 2633 402 (set (reg:SI 147 t)
        (eq:SI (and:SI (reg:SI 2424)
                (reg:SI 2425))
            (const_int 0 [0]))) ../../ORIG/trunk/libiberty/regex.c:7109 1
{tstsi_t}
     (expr_list:REG_DEAD (reg:SI 2425)
        (expr_list:REG_DEAD (reg:SI 2424)
            (nil))))

In insn 10503 reg 2424 will be allocated to R0 and will remain live until insn
10507.  Reload then fails to insert a move insn R0 -> other reg after insn
10503 and R0 allocation for insn 10505 becomes impossible.  I've observed this
issue already a while ago.  I think this condition can be improved using some
sort of linear register allocator for R0-insns.