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[Bug target/64477] [4.9/5 Regression] x86 sse unnecessary GPR spill
- From: "ubizjak at gmail dot com" <gcc-bugzilla at gcc dot gnu dot org>
- To: gcc-bugs at gcc dot gnu dot org
- Date: Wed, 21 Jan 2015 21:48:01 +0000
- Subject: [Bug target/64477] [4.9/5 Regression] x86 sse unnecessary GPR spill
- Auto-submitted: auto-generated
- References: <bug-64477-4 at http dot gcc dot gnu dot org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64477
--- Comment #6 from UroÅ Bizjak <ubizjak at gmail dot com> ---
(In reply to Jakub Jelinek from comment #5)
> Uros, your thoughts on this?
All these *r are (were?) necessary for TARGET_INTER_UNIT_MOVES_{TO,FROM}_VEC to
avoid allocating general reg, but to go through memory.
It looks that this particular case is just an oversight, and this alternative
should be defined as (Yi/r/C), as is the case for similar sse2_loadd insn
Otherwise, these constraints were carefully fine-tuned for reload. IRA is
slightly different, and no wonder that these constraints will have to be
re-tuned in coming years.