[Bug target/64477] [4.9/5 Regression] x86 sse unnecessary GPR spill

["vmakarov at gcc dot gnu.org" <gcc-bugzilla at gcc dot gnu dot org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64477

--- Comment #3 from Vladimir Makarov <vmakarov at gcc dot gnu.org> ---
I investigated this problem too.  IRA in GCC-4.9 allocates memory to the pseudo
in insn 2, then the memory slot is reloaded for insn 8.  Post-reload
optimization changes stack slot by register.

GCC-4.8 IRA allocates a register to the pseudo.  So the behaviour difference
starts in IRA.

I believe that DSE after RA should remove the store.  But the DSE optimization
algorithm is too simple.  It does not work for example with stack-pointer
addressed memory (only with frame-pointer addressed memory).  And x86-64 uses a
 stack-based addresses for stack slots by default.  Even if DSE were able to
work with stack-based addresses, I guess it also can not handle stack slot
sharing (it means we need CFG-sensitive global DSE).

This particular problem could be solved in IRA or in DSE.  I'll try to
investigate what can I do to fix it in IRA.  Still I belive we need much better
RTL-level DSE (dealing with stack-addressed memory slots, global and
CFG-sensitive DSE).