[Bug rtl-optimization/64537] Aarch64 redundant sxth instruction gets generated

["rearnsha at gcc dot gnu.org" <gcc-bugzilla at gcc dot gnu dot org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64537

--- Comment #4 from Richard Earnshaw <rearnsha at gcc dot gnu.org> ---
b is used twice, once shifted left by 3 and once directly.

We could write this as

        subs    x3, x0, x1, sxth 3 
        beq     .L5
        add     w0, w2, w1, sxth          <= Now extended
        add     w0, w0, w3
        ret
        .p2align 2
.L5:
        add     w0, w2, w0
        ret

which in this specific case would perhaps be more efficient, but in practice
it's quite hard to get this sort of multiple-use right.

I think this is a special case, however, of the more common 'un-cse' type of
problem, where multiple uses of an extended (or shifted) value are always
commoned up.

Note that modern CPUs may take an extra cycle to perform an ALU-with-shift type
operation, eliminating the benefit of sinking multiple uses down into the ALU
operations themselves.