[Bug target/53513] New: SH Target: Add support for fschg and fpchg insns

["olegendo at gcc dot gnu.org" <gcc-bugzilla at gcc dot gnu dot org>]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53513

             Bug #: 53513
           Summary: SH Target: Add support for fschg and fpchg insns
    Classification: Unclassified
           Product: gcc
           Version: 4.8.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
        AssignedTo: unassigned@gcc.gnu.org
        ReportedBy: olegendo@gcc.gnu.org
                CC: kkojima@gcc.gnu.org
            Target: sh*-*-*


Currently FPU mode switches are done by always loading values from the global
__fpscr_values array into FPSCR.
On SH4A the fpchg insn should be used to do SFmode / DFmode switches.
On non-SH4A it would probably be better to toggle the PR bit by other means in
order to preserve the other FPSCR bits.  One example use case where the
FPSCR.FR bit needs to be preserved is matrix multiplication, where user code
could swap the register bank using the frchg insn.  Even if the user code
updated the global __fpscr_values to reflect the FPSCR.FR change, it would
break when there are multiple threads that want to use different FPSCR.FR/PR/SZ
settings, as there is only one global __fpscr_values array.

To provide some backwards compatibility with existing binaries the global
__fpscr_values should be kept around.  Old code would then still be able to
reference them and new code would not touch them except when __set_fpscr is
used.  Since the FPSCR.PR/SZ settings at function entry and function exit are
defined by the selected ABI there should be no interoperability problems.