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[Bug target/53133] XOR AL,AL to zero lower 8 bits of EAX/RAX causes partial register stall (Intel Core 2)
- From: "hjl.tools at gmail dot com" <gcc-bugzilla at gcc dot gnu dot org>
- To: gcc-bugs at gcc dot gnu dot org
- Date: Tue, 01 May 2012 16:42:32 +0000
- Subject: [Bug target/53133] XOR AL,AL to zero lower 8 bits of EAX/RAX causes partial register stall (Intel Core 2)
- Auto-submitted: auto-generated
- References: <bug-53133-4@http.gcc.gnu.org/bugzilla/>
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53133
--- Comment #4 from H.J. Lu <hjl.tools at gmail dot com> 2012-05-01 16:42:32 UTC ---
(In reply to comment #2)
> However, Core architecture is not listed under X86_TUNE_PARTIAL_REG_STALL,
> although my documentation says that following latency should be added due to
> partial reg stall:
>
> PPro, P2, P3 : 5
> Core : 1-5
> Core2, Corei7 : 1-6
>
> H.J., should we consider these processors as affected by partial reg stall?
8bit/16bit load ops need to save and restore the upper bits when
updating the lower 8bits/16bits. They are expensive ops on Intel
Core, Core 2 and Core i7 processors. We will check the overall
impact of X86_TUNE_PARTIAL_REG_STALL on Core i7.