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[Bug rtl-optimization/52250] [4.7 Regression] ICE: in sel_remove_bb, at sel-sched-ir.c:5213 with -fsel-sched-pipelining -fsel-sched-pipelining-outer-loops -fselective-scheduling2 and other flags
- From: "abel at gcc dot gnu.org" <gcc-bugzilla at gcc dot gnu dot org>
- To: gcc-bugs at gcc dot gnu dot org
- Date: Tue, 28 Feb 2012 09:04:46 +0000
- Subject: [Bug rtl-optimization/52250] [4.7 Regression] ICE: in sel_remove_bb, at sel-sched-ir.c:5213 with -fsel-sched-pipelining -fsel-sched-pipelining-outer-loops -fselective-scheduling2 and other flags
- Auto-submitted: auto-generated
- References: <bug-52250-4@http.gcc.gnu.org/bugzilla/>
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=52250
Andrey Belevantsev <abel at gcc dot gnu.org> changed:
What |Removed |Added
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CC| |amonakov at gcc dot gnu.org
--- Comment #7 from Andrey Belevantsev <abel at gcc dot gnu.org> 2012-02-28 09:04:46 UTC ---
It should be possible to bootstrap, we generally keep an eye on it. Last time
we did benchmarking I think was when Alexander implemented predication support,
as it works on x86-64 as well (and helps pipelining there, too). Probably the
slight improvement wasn't worth the slowdown, but Alexander should remember
better for sure. And of course this can be re-benchmarked on Stage 1 with
predication committed and enabled.