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[Bug target/29560] [avr] Poor optimization for byte shifts
- From: "gjl at gcc dot gnu.org" <gcc-bugzilla at gcc dot gnu dot org>
- To: gcc-bugs at gcc dot gnu dot org
- Date: Sat, 23 Jul 2011 14:51:28 +0000
- Subject: [Bug target/29560] [avr] Poor optimization for byte shifts
- Auto-submitted: auto-generated
- References: <bug-29560-4@http.gcc.gnu.org/bugzilla/>
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=29560
--- Comment #7 from Georg-Johann Lay <gjl at gcc dot gnu.org> 2011-07-23 14:50:58 UTC ---
Created attachment 24816
--> http://gcc.gnu.org/bugzilla/attachment.cgi?id=24816
Test case for 16-bit shifts that use low part only
Reopened this optimization issue.
For the attached test case, there are sometimes REG_UNUSED notes for the high
part like with avr-gcc-4.6.1 -Os -dP
shift1:
; (insn 8 4 17 (set (reg:HI 24 r24 [50])
; (ashift:HI (reg:HI 24 r24 [ x ])
; (reg/v:QI 22 r22 [orig:47 s ] [47]))) foo.c:3 68 {ashlhi3}
; (expr_list:REG_DEAD (reg/v:QI 22 r22 [orig:47 s ] [47])
; (expr_list:REG_UNUSED (reg:QI 25 r25)
; (nil))))
rjmp 2f ; 8 ashlhi3/1 [length = 6]
1: lsl r24
rol r25
2: dec r22
brpl 1b
So that there is a way to map ashlhi3 to ashlqi3, i.e. 16-bit shift to a 8-bit
shift.
Unfortunately, these notes are not always present like in shift2:
shift2:
; (insn 15 4 8 (set (reg:HI 18 r18)
; (reg:HI 24 r24 [ x ])) foo.c:10 10 {*movhi}
; (nil))
movw r18,r24 ; 15 *movhi/1 [length = 1]
; (insn 8 15 9 (set (reg:HI 18 r18)
; (ashift:HI (reg:HI 18 r18)
; (reg/v:QI 22 r22 [orig:46 s ] [46]))) foo.c:10 68 {ashlhi3}
; (expr_list:REG_DEAD (reg/v:QI 22 r22 [orig:46 s ] [46])
; (nil)))
rjmp 2f ; 8 ashlhi3/1 [length = 6]
1: lsl r18
rol r19
2: dec r22
brpl 1b
The notes are not present in pass .split2 so a split won't help. The notes
appear to be available in .peephole2 so that could be a fix. Moreover, the
notes won't be back-propagated so that an optimization will cover at most one
insn: the shift insn.