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[Bug target/41176] [4.4/4.5 Regression] ICE in reload_cse_simplify_operands at postreload.c:396
- From: "uweigand at gcc dot gnu dot org" <gcc-bugzilla at gcc dot gnu dot org>
- To: gcc-bugs at gcc dot gnu dot org
- Date: 8 Oct 2009 18:39:47 -0000
- Subject: [Bug target/41176] [4.4/4.5 Regression] ICE in reload_cse_simplify_operands at postreload.c:396
- References: <bug-41176-271@http.gcc.gnu.org/bugzilla/>
- Reply-to: gcc-bugzilla at gcc dot gnu dot org
------- Comment #9 from uweigand at gcc dot gnu dot org 2009-10-08 18:39 -------
(In reply to comment #8)
> This is on (set (reg:DF X) (mem:DF ((plus:DI (reg:DI Y) (const_int 3)))).
> When X is still a pseudo, this is considered valid, as lfd accept any offset,
> but when RA chooses to assign X to a GPR register, the address doesn't match
> the Y constraint in movdf_hardfloat64. Is this a bug in reload that it doesn't
> attempt to force the address into a register, or in target description that it
> should tell reload to do so somehow? Or does the backend need to be able to
> handle these, perhaps by forcing splitting of it?
If reload were fixing up this insn, it would indeed have to make sure that
the Y -> r constraints are respected, e.g. by reloading the address.
However, this whole insn is *generated* by reload, in order to load a
value into a reload register. Unfortunately, for such reload insns
(which are simple moves), reload will simply assume they must be supported
by the target, unless there is a secondary reload for this case.
To fix this, I guess the rs6000 backend either has to accept the insn
and implement it via splitting, or else register a secondary reload for
this case (which is also able to request scratch registers).
--
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=41176