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[Bug middle-end/37908] [4.2/4.3/4.4 regression] atomic NAND op generate wrong code; __sync_nand_and_fetch, __sync_fetch_and_nand
- From: "kokseng at ieee dot org" <gcc-bugzilla at gcc dot gnu dot org>
- To: gcc-bugs at gcc dot gnu dot org
- Date: 24 Oct 2008 12:18:08 -0000
- Subject: [Bug middle-end/37908] [4.2/4.3/4.4 regression] atomic NAND op generate wrong code; __sync_nand_and_fetch, __sync_fetch_and_nand
- References: <bug-37908-16859@http.gcc.gnu.org/bugzilla/>
- Reply-to: gcc-bugzilla at gcc dot gnu dot org
------- Comment #4 from kokseng at ieee dot org 2008-10-24 12:18 -------
Okay, now I noticed the 'nand' comment on the documentation for atomic
builtins, the code does implement the 'negate and AND' logic, which is named
'nand'.
On page 164 of icc "Intrinsics Reference"
(http://softwarecommunity.intel.com/isn/downloads/softwareproducts/pdfs/347603.pdf),
ti does not have such qualifier that 'nand' is not NAND, but negate-and-AND.
I do not have any further evidence how icc actually implement __sync_*nand*.
This came about when adding unit-test on atomic operation for purpose of
trapping problems when porting across platform.
I wonder why the overloading of 'nand' ?
--
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=37908