[Bug middle-end/37243] [4.4 Regression] IRA causes wrong code generation

["hjl dot tools at gmail dot com" <gcc-bugzilla at gcc dot gnu dot org>]

------- Comment #22 from hjl dot tools at gmail dot com  2008-09-03 16:05 -------
(In reply to comment #7)
> Created an attachment (id=16155)
 --> (http://gcc.gnu.org/bugzilla/attachment.cgi?id=16155&action=view) [edit]
> Test case from 2006.434.zeusmp
> 
> Though fail to extract a smaller case, hopeful it helpful.
> 
> Compile with gfortran -c -O2 -DSPEC_CPU_LP64 tranx1.f -S -fdump-rtl-all -g.
> Miscompile in revision 139590.
> 
> In IRA dump file, I believe following suspicious RTL is the cause of segfault:
> (insn 886 885 893 35 tranx1.f:570 (set (reg:DI 0 ax [orig:123 D.3215 ] [123])
>         (mem/c:DI (plus:DI (reg/f:DI 7 sp)
>                 (const_int -104 [0xffffffffffffff98])) [68 D.3215+0 S8 A64]))
> 89 {*movdi_1_rex64} (nil))
> 
> (insn 893 886 896 35 tranx1.f:570 (set (mem/c:DI (plus:DI (reg/f:DI 7 sp)
>                 (const_int -104 [0xffffffffffffff98])) [68 ivtmp.160+0 S8 A64])
>         (reg/f:DI 3 bx [orig:159 ivtmp.160 ] [159])) 89 {*movdi_1_rex64} (nil))
> D.3215 and ivtmp.160 shares the spill space (%rsp-104), where as D.3215 and
> ivtmp.160 has overlapped liverange.
> 

It is fixed by Richard's use DF patch:

http://gcc.gnu.org/ml/gcc/2008-09/msg00015.html


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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=37243