[Bug rtl-optimization/33922] [4.3 Regression] slow compilation on ia64 (postreload scheduling)

["jakub at gcc dot gnu dot org" <gcc-bugzilla at gcc dot gnu dot org>]

------- Comment #19 from jakub at gcc dot gnu dot org  2007-10-28 20:42 -------
Another trivial patch that improves speed is:
--- ia64.c      (revision 129700)
+++ ia64.c      (working copy)
@@ -5310,11 +5310,11 @@ ia64_safe_type (rtx insn)

 struct reg_write_state
 {
-  unsigned int write_count : 2;
-  unsigned int first_pred : 16;
-  unsigned int written_by_fp : 1;
-  unsigned int written_by_and : 1;
-  unsigned int written_by_or : 1;
+  unsigned short write_count : 2;
+  unsigned short first_pred : 10;
+  unsigned short written_by_fp : 1;
+  unsigned short written_by_and : 1;
+  unsigned short written_by_or : 1;
 };

 /* Cumulative info for the current instruction group.  */

which cuts the size of rws_sum and rws_saved arrays into half (1604 to 802
bytes)
and with both patches in I get:
 scheduling 2          :   6.86 (82%) usr   0.01 (50%) sys   6.87 (82%) wall   
1970 kB (15%) ggc

or 31% speedup in wall time both patches together.  first_pred is either 0 or
PR_REG(0) through PR_REG(63), so it certainly fits into 10 bit bitfield.  If
needed it would fit even into 6 bit (as when pred == 0, write_count will be
already 2 and we could subtract PR_REG(0) from it), but that's still too big to
squeeze it into 1 byte per register.

Even when this bug is fixed for real, both changes IMHO make sense anyway (the
first patch could perhaps use some cleanup, nice macros to hide it or
something).


-- 


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=33922