[Bug target/32661] __builtin_ia32_vec_ext suboptimal for pointer/ref args

["ubizjak at gmail dot com" <gcc-bugzilla at gcc dot gnu dot org>]

------- Comment #7 from ubizjak at gmail dot com  2007-07-13 06:08 -------
I have following patch that solves nested VEC_SELECT insn. However, I would
like to enhance it for nested VEC_SELECT (VEC_SELECT (VEC_DUPLICATE (...)))
that is generated i.e. for __builtin_ia32_vec_ext_v4si(*val, 2);

Index: simplify-rtx.c
===================================================================
--- simplify-rtx.c      (revision 126587)
+++ simplify-rtx.c      (working copy)
@@ -2669,6 +2669,31 @@ simplify_binary_operation_1 (enum rtx_co
          if (GET_CODE (trueop0) == CONST_VECTOR)
            return CONST_VECTOR_ELT (trueop0, INTVAL (XVECEXP
                                                      (trueop1, 0, 0)));
+         if (GET_CODE (trueop0) == VEC_SELECT
+             && (GET_MODE (XEXP (trueop0, 0)) == GET_MODE (trueop0)))
+           {
+             rtx op = XEXP (trueop0, 0);
+             rtx sel = XEXP (trueop0, 1);
+             enum machine_mode opmode = GET_MODE (op);
+             rtvec vec;
+             rtx tmp;
+
+             int elt_size = GET_MODE_SIZE (GET_MODE_INNER (opmode));
+             int n_elts = GET_MODE_SIZE (opmode) / elt_size;
+
+             int i = INTVAL (XVECEXP (trueop1, 0, 0));
+
+             gcc_assert (GET_CODE (sel) == PARALLEL);
+             gcc_assert (i < n_elts);
+
+             /* Select value, pointed by nested selector.  */
+             vec = rtvec_alloc (1);
+             RTVEC_ELT (vec, 0) = CONST_VECTOR_ELT (sel, i);
+             tmp = gen_rtx_PARALLEL (VOIDmode, vec);
+
+             tmp = gen_rtx_fmt_ee (code, mode, op, tmp);
+             return tmp;
+           }
        }
       else
        {
Index: config/i386/sse.md
===================================================================
--- config/i386/sse.md  (revision 126587)
+++ config/i386/sse.md  (working copy)
@@ -4578,6 +4578,22 @@
   operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]));
 })

+(define_insn_and_split "*sse2_stored_1"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+       (vec_select:SI
+         (match_operand:V4SI 1 "memory_operand" "o")
+         (parallel [(match_operand 2 "const_0_to_3_operand" "")])))]
+  "TARGET_SSE"
+  "#"
+  "&& reload_completed"
+  [(const_int 0)]
+{
+  int i = INTVAL (operands[2]);
+
+  emit_move_insn (operands[0], adjust_address (operands[1], SImode, i*4));
+  DONE;
+})
+
 (define_expand "sse_storeq"
   [(set (match_operand:DI 0 "nonimmediate_operand" "")
        (vec_select:DI


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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=32661