This is the mail archive of the mailing list for the GCC project.

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

[Bug tree-optimization/23346] [4.1/4.2 Regression] FRE before DCE makes a mess of loads or need to sink loads

------- Comment #13 from rguenth at gcc dot gnu dot org  2006-10-10 11:58 -------
On mainline we now have

        xorl    %eax, %eax
        movl    a, %edx
        cmpl    $0, 4(%esp)
        movl    b, %ecx
        jne     .L4
        movl    %edx, %eax
        sarl    $31, %edx
        idivl   %ecx
        rep ; ret

which still loads a and b unconditionally, but it looks less "messy".  4.1.1
is the mess as in comment #1.

We end up with

f (bool1)
  int c1;
  int c;
  int b.1;
  int a.0;

<bb 2>:
  #   VUSE <a_2>;
  a.0_3 = a;
  #   VUSE <b_4>;
  b.1_5 = b;
  if (bool1_7 != 0) goto <L2>; else goto <L1>;

  c1_6 = a.0_3 / b.1_5;

  # c_1 = PHI <0(2), c1_6(3)>;
  return c_1;


where the best thing would be to sink the loads to the single-use a.0_3 and
b.1_5 into the conditional BB.  It looks like TER has code to deal with this
case and could replace a.0_3 and b.1_5 with a and b, but this doesn't happen.


rguenth at gcc dot gnu dot org changed:

           What    |Removed                     |Added
                 CC|                            |amacleod at redhat dot com
   Last reconfirmed|2006-07-05 09:35:27         |2006-10-10 11:58:07
               date|                            |

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]