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[Bug target/29314] misaligned FP register for VIS instructions
- From: "ebotcazou at gcc dot gnu dot org" <gcc-bugzilla at gcc dot gnu dot org>
- To: gcc-bugs at gcc dot gnu dot org
- Date: 2 Oct 2006 06:37:16 -0000
- Subject: [Bug target/29314] misaligned FP register for VIS instructions
- References: <bug-29314-6365@http.gcc.gnu.org/bugzilla/>
- Reply-to: gcc-bugzilla at gcc dot gnu dot org
------- Comment #1 from ebotcazou at gcc dot gnu dot org 2006-10-02 06:37 -------
With mainline:
poog% gcc/xgcc -Bgcc -c pr29314.c -mvis -mcpu=ultrasparc -O2
/usr/ccs/bin/as: "/var/tmp//ccPi3BER.s", line 12: error: invalid (misaligned)
register
/usr/ccs/bin/as: "/var/tmp//ccPi3BER.s", line 14: error: invalid (misaligned)
register
--
ebotcazou at gcc dot gnu dot org changed:
What |Removed |Added
----------------------------------------------------------------------------
CC| |ebotcazou at gcc dot gnu dot
| |org
Status|UNCONFIRMED |NEW
Ever Confirmed|0 |1
Last reconfirmed|0000-00-00 00:00:00 |2006-10-02 06:37:16
date| |
Summary|SPARC V9 uses bad FP |misaligned FP register for
|register for VIS |VIS instructions
|instructions |
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=29314