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[Bug target/14552] compiled trivial vector intrinsic code is ineffiencent
- From: "uros at kss-loka dot si" <gcc-bugzilla at gcc dot gnu dot org>
- To: gcc-bugs at gcc dot gnu dot org
- Date: 15 Sep 2005 11:39:39 -0000
- Subject: [Bug target/14552] compiled trivial vector intrinsic code is ineffiencent
- References: <20040312131535.14552.michaelni@gmx.at>
- Reply-to: gcc-bugzilla at gcc dot gnu dot org
------- Additional Comments From uros at kss-loka dot si 2005-09-15 11:39 -------
(In reply to comment #14)
> Yes, it does not work when configuring gcc with --with-cpu=pentium4 see PR
19161.
No, the patch works OK for pentium4. The remaining problem is in
optimize_mode_switching() function. For a certain loop layout, o_m_s could
insert emms and efpu insn in such way, that both register sets are blocked.
Because emms/efpu insertion depends heavily on o_m_s functionality, this
infrastructure should be upgraded as explained in PR 19161.
(BTW: One of the design goals was to ICE, instead of generating wrong code. It
loks that this goal was achieved :)
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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=14552