[Bug target/23303] [4.1 Regression] 4.1 generates sall + addl instead of leal

["bonzini at gcc dot gnu dot org" <gcc-bugzilla at gcc dot gnu dot org>]

------- Additional Comments From bonzini at gcc dot gnu dot org  2005-08-22 11:01 -------
I'm not confident that using salq in Steven's test case is really a
pessimization.  I'll consider a 32-bit target then, and this testcase

  char **
  VTallocbuf(char **allbuf, unsigned long savelines)
  {
    return &allbuf[savelines];
  }

For i686 we have

        movl    8(%esp), %eax
        movl    4(%esp), %edx
        sall    $2, %eax
        addl    %edx, %eax

instead of

        movl    8(%esp), %eax
        movl    4(%esp), %edx
        leal    (%edx,%eax,4), %eax

However even in this case a no-lea code could be feasible:

        movl    8(%esp), %eax
        sall    $2, %eax
        addl    4(%esp), %eax

And this is exactly the rtl we have until peephole2, where this peephole splits
the instruction:

;; Don't do logical operations with memory inputs.
(define_peephole2
  [(match_scratch:SI 2 "r")
   (parallel [(set (match_operand:SI 0 "register_operand" "")
                   (match_operator:SI 3 "arith_or_logical_operator"
                     [(match_dup 0)
                      (match_operand:SI 1 "memory_operand" "")]))
              (clobber (reg:CC FLAGS_REG))])]
  "! optimize_size && ! TARGET_READ_MODIFY"
  [(set (match_dup 2) (match_dup 1)) 
   (parallel [(set (match_dup 0)
                   (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
              (clobber (reg:CC FLAGS_REG))])]
  "")

I think that Jan's patch should be conditionalized: if !optimize_size &&
!TARGET_READ_MODIFY, the transformation he removed will be done anyway, and too
late in the game.

Paolo

-- 


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=23303