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[Bug tree-optimization/18463] [4.0/4.1 Regression] suboptimal use of fancy x86 addressing modes
- From: "jh at suse dot cz" <gcc-bugzilla at gcc dot gnu dot org>
- To: gcc-bugs at gcc dot gnu dot org
- Date: 13 Jun 2005 13:40:44 -0000
- Subject: [Bug tree-optimization/18463] [4.0/4.1 Regression] suboptimal use of fancy x86 addressing modes
- References: <20041113170938.18463.steven@gcc.gnu.org>
- Reply-to: gcc-bugzilla at gcc dot gnu dot org
------- Additional Comments From jh at suse dot cz 2005-06-13 13:40 -------
Subject: Re: [4.0/4.1 Regression] suboptimal use of fancy x86 addressing modes
>
> ------- Additional Comments From pinskia at gcc dot gnu dot org 2005-06-13 12:46 -------
> On the mainline we get now:
> .L4:
> movl (%ebp,%edx,4), %eax
> movl %eax, (%ebx,%edx,4)
> movl (%esi,%edx,4), %eax
> movl %eax, (%ecx,%edx,4)
> incl %edx
> cmpl %edx, %edi
> jne .L4
>
> Which is better but the two loads/stores are not scheduled.
-frename-registers? But hardware will do that for you anyway.
Honza
>
> --
>
>
> http://gcc.gnu.org/bugzilla/show_bug.cgi?id=18463
>
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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=18463