[Bug target/19530] MMX load intrinsic produces SSE superfluous instructions (movlps)

["guardia at sympatico dot ca" <gcc-bugzilla at gcc dot gnu dot org>]

------- Additional Comments From guardia at sympatico dot ca  2005-01-27 22:55 -------
I think I'm starting to see the problem here... I tried to understand more of
the code, and from this and what you tell me, gcc find registers to use and then
finds instructions to that fits the bill. So preventing gcc from using some
instructions will only end up in a "instruction not found" error. The register
allocator is the one that shouldn't allocate them in the first place, right?

Well, let's forget this for now... maybe we should look at the optimization stages:
        movq    %mm0, -8(%ebp)
        movlps  -8(%ebp), %xmm1
        movlps  %xmm1, (%eax)
<- If movlps merely moves 64 bit stuff around, why wasn't it optimized out to a
one equivalent movq that also moves 64 bit stuff around? Would that be an
optimizer problem instead?

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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=19530