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[Bug target/19235] [4.0 regression] GCC generates SSE2 instructions for AthlonXP which doesn't support them.
- From: "drab at kepler dot fjfi dot cvut dot cz" <gcc-bugzilla at gcc dot gnu dot org>
- To: gcc-bugs at gcc dot gnu dot org
- Date: 3 Jan 2005 15:34:37 -0000
- Subject: [Bug target/19235] [4.0 regression] GCC generates SSE2 instructions for AthlonXP which doesn't support them.
- References: <20050103020419.19235.drab@kepler.fjfi.cvut.cz>
- Reply-to: gcc-bugzilla at gcc dot gnu dot org
------- Additional Comments From drab at kepler dot fjfi dot cvut dot cz 2005-01-03 15:34 -------
(In reply to comment #6)
> The patch does not fix the problem; the xmm registers are used anyway...
SSE instructions also use the xmm registers! The problem wasn't in using the xmm
registers (frankly, I hope it will accelerate things a bit by using the SSE to
copy), but problem was, that those "f3 0f 7e ..." and "66 0f d6 ..."
instructions (that's why I listed it with objdump) belong to the to the SSE2
instruction set. If instead it would use the instructions from SSE only (also
with xmm regs. of course), that would be good.
--
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=19235