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[Bug middle-end/18641] [4.0 Regression] Another ICE caused by reload of a psuedo reg into f0 for a DImode expr
- From: "cvs-commit at gcc dot gnu dot org" <gcc-bugzilla at gcc dot gnu dot org>
- To: gcc-bugs at gcc dot gnu dot org
- Date: 11 Dec 2004 17:37:36 -0000
- Subject: [Bug middle-end/18641] [4.0 Regression] Another ICE caused by reload of a psuedo reg into f0 for a DImode expr
- References: <20041124011632.18641.fjahanian@apple.com>
- Reply-to: gcc-bugzilla at gcc dot gnu dot org
------- Additional Comments From cvs-commit at gcc dot gnu dot org 2004-12-11 17:37 -------
Subject: Bug 18641
CVSROOT: /cvs/gcc
Module name: gcc
Changes by: dje@gcc.gnu.org 2004-12-11 17:37:26
Modified files:
gcc : ChangeLog
gcc/config/rs6000: darwin.h rs6000.h rs6000.md
Log message:
2004-12-11 David Edelsohn <edelsohn@gnu.org>
Ulrich Weigand <uweigand@de.ibm.com>
PR target/18641
* config/rs6000/darwin.h (PREFERRED_RELOAD_CLASS): Reload all
constants into all register classes intersecting with FLOAT_REGS
via memory.
* config/rs6000/rs6000.h (PREFERRED_RELOAD_CLASS): Same.
* config/rs6000/rs6000.md (movdi_internal32): Ignore FPRs when
choosing register preferences.
(movdi_internal64): Same.
Patches:
http://gcc.gnu.org/cgi-bin/cvsweb.cgi/gcc/gcc/ChangeLog.diff?cvsroot=gcc&r1=2.6782&r2=2.6783
http://gcc.gnu.org/cgi-bin/cvsweb.cgi/gcc/gcc/config/rs6000/darwin.h.diff?cvsroot=gcc&r1=1.73&r2=1.74
http://gcc.gnu.org/cgi-bin/cvsweb.cgi/gcc/gcc/config/rs6000/rs6000.h.diff?cvsroot=gcc&r1=1.348&r2=1.349
http://gcc.gnu.org/cgi-bin/cvsweb.cgi/gcc/gcc/config/rs6000/rs6000.md.diff?cvsroot=gcc&r1=1.336&r2=1.337
--
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=18641