[Bug target/15598] [3.4 Regression]: Gcc 3.4 ICE on valid code

["wilson at specifixinc dot com" <gcc-bugzilla at gcc dot gnu dot org>]

------- Additional Comments From wilson at specifixinc dot com  2004-06-08 07:33 -------
Subject: Re:  [3.4 Regression]: Gcc 3.4 ICE on valid code

hjl at lucon dot org wrote:
>         * config/ia64/itanium1.md (1_ialu_addr): Also allow I-unit.
>         (1b_ialu_addr): Likewise.

I do not believe this patch is correct.  I believe the 1*_ialu_addr 
patterns are deliberately using M instead of A.

Use of M instead of A restricts bundling unnecessarily, however, it 
allows us to accurately model the latency of the operation, which is 
particularly important when we have an ialu instruction that generates a 
load/store address.

Use of A would not restrict bundling, but would not let us model 
latencies accurately.  An insn can only have one latency, but the 
latency of an ialu insn varies depending on whether it gets scheduled to 
an M slot or an I slot.

Hence there is a trade off here between getting bundling right or 
getting latencies right.  The code as written gets the latecy right when 
an ialu generates a load/store address, presumably to avoid an AGI 
stall, and gets the bundling right otherwise.


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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=15598