[Bug optimization/13951] [tree-ssa] cselib ICE during x86-64 kernel compile with treessa

["jh at suse dot cz" <gcc-bugzilla at gcc dot gnu dot org>]

------- Additional Comments From jh at suse dot cz  2004-02-04 17:11 -------
Subject: Re:  [tree-ssa] cselib ICE during  x86-64 kernel compile with treessa

> 
> ------- Additional Comments From jh at suse dot cz  2004-02-04 12:11 -------
> Subject: Re:  [tree-ssa] cselib ICE during  x86-64 kernel compile with treessa
> 
> > 
> > ------- Additional Comments From rth at gcc dot gnu dot org  2004-02-04 03:34 -------
> > Jan, I assume this is some bit of cselib changes present on mainline that
> > didn't make it to the branch.  Would you take care of it please?
> 
> I think it is unrelated - nothing of my recent changes shall affect
> something else than schedule-ebbs used only by IA-64, but I plan to look
> into it soon (once I resolve the remaining cgraphunit merge issues)
The problem is:

(insn 154 153 155 13 (parallel [
            (set (reg/v:SI 74 [ eax ])
                (asm_operands:SI ("cpuid") ("=a") 0 [
                        (reg:SI 108)
                    ]
                     [  
                        (asm_input:SI ("0"))
                    ] ("include/asm/msr.h") 72))
            (set (reg/v:SI 73 [ dummy ])
                (asm_operands:SI ("cpuid") ("=b") 1 [
                        (reg:SI 108)
                    ]
                     [  
                        (asm_input:SI ("0"))
                    ] ("include/asm/msr.h") 72))
            (set (reg/v:SI 73 [ dummy ])
                (asm_operands:SI ("cpuid") ("=c") 2 [
                        (reg:SI 108)
                    ]
                     [  
                        (asm_input:SI ("0"))
                    ] ("include/asm/msr.h") 72))
            (set (reg:SI 107)
                (asm_operands:SI ("cpuid") ("=d") 3 [
                        (reg:SI 108)
                    ]
                     [  
                        (asm_input:SI ("0"))
                    ] ("include/asm/msr.h") 72))
            (clobber (reg:QI 19 dirflag))
            (clobber (reg:QI 18 fpsr))
            (clobber (reg:QI 17 flags))
        ]) -1 (nil)
    (nil))

I think CSELIB ICE because dummy is set twice.  I think it makes sense
to do so, but I am unsure where to avoid it.  I will look into it
tomorrow.

Honza


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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=13951