Re: SH target - disable @(r0,rm) addressing mode?

[Joern Rennecke <joern dot rennecke at superh dot com>]

tm_gccmail@mail.kloo.net wrote:
> The generalized @(rm,rn) approach seems better than faking a 3AC add
> because there's only one extra instruction generated versus two.

No, in the example assembler code you posted, most of the r0 values
were calculated with an add at the end.  By allowing a 3-address add,
register allocation would be less inclined to do the entire calculation
in r0; with the two-address add replaced by a three-address add, we'll
end up with one extra instruction, a register-register move in front
of the add, which can be issued in the same cycle as the add itself.

> What are the possible side effects of doing this?
[The generalized @(rm,rn) approach]

Code that expects to be able to generate a move with gen_rtx_SET won't
work.  We already have a clobber in movsf_ie, so thye use of gen_rtx_SET
can't be too widespread - except in loosing optimizers, IIRC gcse was
born with such a birth defect and only got fixed up later.
Things to watch out for is reload trying to load an address the low-level
way.  gen_reload seems to be OK, though - it uses gen_move_insn.
	
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