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SH target - disable @(r0,rm) addressing mode?
- From: <tm_gccmail at mail dot kloo dot net>
- To: joern dot rennecke at superh dot com, aoliva at redhat dot com
- Cc: gcc-bugs at gcc dot gnu dot org
- Date: Tue, 4 Feb 2003 13:08:49 -0800 (PST)
- Subject: SH target - disable @(r0,rm) addressing mode?
I've been looking at some fairly abysmal SH4 code generated for the
stress-1.14
testcase for CVS head with -O2 -m4 -fnew-ra, and here's what I've found.
The basic problem seems to be an overdependency on the dual-register
addressing
mode @(r0,rm). The problem is the first register must be r0, so this leads
to an overusage of r0, which leaves no placement freedom for the
instruction
scheduler. The processor appears to be only single-issuing in large blocks
of code due to this problem.
I'm wondering if we should disable the @(r0,rm) addressing mode except for
special cases such as GOT references. This may sound a little extreme,
but I'm getting tired of fighting the problems associated with this single
register class, and I'd like to solve the problem completely for once.
Any thoughts?
Here's the compiled code for reference:
( yr ^= ((((S[0 * 256 + ((( yl ) >> (24)) & (0x00ff)) ] + S[1 *
256 + ((( yl ) >> (16)) & (0x00ff)) ]) ^ S[2 * 256 + ((( yl ) >>
(8)) & (0x00ff)) ]) + S[3 * 256 + ((( yl ) & 0x00ff)) ]) ^ P[ 1
])) ; ( yl ^= ((((S[0 * 256 + ((( yr ) >> (24)) & (0x00ff)) ] + S[1
* 256 + ((( yr ) >> (16)) & (0x00ff)) ]) ^ S[2 * 256 + ((( yr
) >> (8)) & (0x00ff)) ]) + S[3 * 256 + ((( yr ) & 0x00ff)) ]) ^ P[
2 ])) ;
stream2 = S[((yl >> 24) & 0x00ff)]
stream1 = S[256 + ((yl >> 16) & 0x00ff))]
stream3 = S[512 + ((yl >> 8 ) & 0x0fff))]
stream4 = S[768 + (y1 & 0x00ff)]
12: 99 f7 mov.w 204
<_ssh_blowfish_encrypt+0x204>,r9 ! 0x400
14: 25 1a xor r1,r5
16: 98 f6 mov.w 206
<_ssh_blowfish_encrypt+0x206>,r8 ! 0x800
18: 60 53 mov r5,r0 <- stream 1
1a: 40 29 shlr16 r0 <- stream 1
1c: 6a 53 mov r5,r10 <- stream 2
1e: 60 0c extu.b r0,r0 <- stream 1
20: 4a 29 shlr16 r10 <- stream 2
22: 93 f1 mov.w 208
<_ssh_blowfish_encrypt+0x208>,r3 ! 0xc00
24: 4a 19 shlr8 r10 <- stream 2
26: 51 21 mov.l @(4,r2),r1
28: 40 08 shll2 r0 <- stream 1
2a: 30 4c add r4,r0 <- stream 1
2c: 4a 08 shll2 r10
2e: 2e 02 mov.l r0,@r14 <- stream 1
30: 60 a3 mov r10,r0
32: 0a 4e mov.l @(r0,r4),r10
34: 60 e6 mov.l @r14+,r0 <- stream 1
36: 00 9e mov.l @(r0,r9),r0 <- stream 1
38: 3a 0c add r0,r10 <- stream 1
3a: 60 53 mov r5,r0 <- stream 3
3c: 40 19 shlr8 r0 <- stream 3
3e: 60 0c extu.b r0,r0 <- stream 3
40: 40 08 shll2 r0 <- stream 3
42: 30 4c add r4,r0 <- stream 3
44: 00 8e mov.l @(r0,r8),r0 <- stream 3
46: 2a 0a xor r0,r10 <- stream 3
48: 60 5c extu.b r5,r0 <- stream 4
4a: 40 08 shll2 r0 <- stream 4
4c: 30 4c add r4,r0 <- stream 4
4e: 00 3e mov.l @(r0,r3),r0 <- stream 4
50: 3a 0c add r0,r10 <- stream 4
52: 2a 1a xor r1,r10
...
Toshi