bug in cse elimination

["Mark S Dettinger" <DETTINGE at de dot ibm dot com>]

The CSE elimination of gcc contains a conceptual bug:

Assume the RTL code contains the following RTXes:

(set (reg:DI 40) (reg:DI 2))
(set (reg:SI 42) (reg:SI 2))
(set (mem:SI (some address)) (reg:SI 42))

Register 2 is a hard register and can be accessed in both SI and DI mode,
(reg:DI 40) and (reg:SI 42) are pseudo-registers and can only be accessed
in one mode.

At the first rtx, the function make_reg_eqv(40,2) is called
and puts the registers 40 2 in the same equivalence chain.
This is legal, since the registers 40 and 2 are both accessed in DI mode.

At the second rtx, the function make_reg_eqv(42,2) is called
and inserts register 42 into the equivalence chain of register 2.
Although 42 and 2 are both accessed in SI mode, this operation
is not legal, because now the chain contains three registers: 2, 40, and
42.
However, (reg:DI 40) and (reg:SI 42) should never be in the same chain.

Now, at the third rtx, the compiler _could_ crash, if gcc decides to
replace
(reg:SI 42) by (reg:DI 40). This would lead to an "Illegal instruction"
internal error in a later phase.

Do you have any suggestions how to fix this problem?
Should the second call to make_reg_eqv (in the example above)
create a second equivalence chain with the registers 42 and 2?
But then register 2 would appear in two chains at the same time
which might cause other problems.

-Mark