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SH4 SFmode move latency problem?
- From: tm <tm at mail dot kloo dot net>
- To: joern dot rennecke at superh dot com
- Cc: gcc-bugs at gcc dot gnu dot org
- Date: Fri, 8 Nov 2002 16:52:18 -0800 (PST)
- Subject: SH4 SFmode move latency problem?
I'm noticing something weird about the SH4 SFmode register-to-register
moves. Here's a sample:
.L8:
fmov fr12,fr6
mov #0,r0
fmov fr13,fr7
fmov fr10,fr2
fmov fr11,fr3
fmul dr12,dr6
fmov fr14,fr0
fmov fr15,fr1
The "fmul dr12,dr6" instruction is dependent on the two instructions
"fmov fr12,fr6" and "fmov fr13,fr7" because dr6 are the two registers
fr6 and fr7 combined.
The SH4 is a dual-issue in-order implementation and the SFmode
register-to-register moves have an issue rate of 1 and a latency of
zero. This means the "fmul dr12,dr6" instruction is ready to issue in the
same clock as the "fmov fr13,fr7" instruction.
However, the instruction scheduler is placing the multiply instruction
three instructions after the last flow dependent instruction.
This is very strange, and might be degrading performance on the SH4?
Toshi