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Re: [avr-gcc-list] avr 32 bit math bug
- From: "David Breeze" <DBreeze at joy dot co dot uk>
- To: <avr-gcc-list at avr1 dot org>, <sjackman at shaw dot ca>
- Cc: <gcc-bugs at gcc dot gnu dot org>
- Date: Fri, 04 Oct 2002 10:19:35 +0100
- Subject: Re: [avr-gcc-list] avr 32 bit math bug
Hi shaun
Unless you have disabled the normal preamble, r1 is generally the zero register and is loaded very early in the program.
sbiw and sbc both clear or set the carry as a result of the subtraction, so
sbc r26,r1 is simply subtracting the carry if set.
DaveB
>>> Shaun Jackman <sjackman@shaw.ca> 04 October 2002 09:26:10 >>>
I've found two 32 bit math bugs in avr-gcc. Try the following code...
uint32_t delay = 500000;
while( --delay);
produces...
delay = 500000;
64: 80 e2 ldi r24, 0x20 ; 32
66: 91 ea ldi r25, 0xA1 ; 161
68: a7 e0 ldi r26, 0x07 ; 7
6a: b0 e0 ldi r27, 0x00 ; 0
while( --delay);
6c: 01 97 sbiw r24, 0x01 ; 1
6e: a1 09 sbc r26, r1
70: b1 09 sbc r27, r1
72: e1 f7 brne .-8 ; 0x6c
74: cc cf rjmp .-104 ; 0xe
There's two problems with this.
1. sbiw and sbc clear the zero flag, but they never set it!
2. r1 is used as a source register, but it's never initialized!
I had to work around it like this...
uint32_t delay = 500000;
asm( "clr r1");
while( --delay)
asm( "sez\n");
produces...
12: 11 24 eor r1, r1
while( --delay)
14: 8f e0 ldi r24, 0x0F ; 15
16: 97 e2 ldi r25, 0x27 ; 39
18: a0 e0 ldi r26, 0x00 ; 0
1a: b0 e0 ldi r27, 0x00 ; 0
asm( "sez\n");
1c: 18 94 sez
1e: 01 97 sbiw r24, 0x01 ; 1
20: a1 09 sbc r26, r1
22: b1 09 sbc r27, r1
24: d9 f7 brne .-10 ; 0x1c
26: f3 cf rjmp .-26 ; 0xe
Anyone seen this before?
avr-elf-gcc (GCC) 3.2 (Debian)
avr-elf-gcc -g -O2 -mmcu=at90s8515 foo.c -o foo
Thanks,
Shaun
avr-gcc-list at http://avr1.org
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