This is the mail archive of the
gcc-bugs@gcc.gnu.org
mailing list for the GCC project.
bug with instruction set
- From: "MASSON François" <tereutes at freesurf dot fr>
- To: <bug-gcc at gnu dot org>
- Date: Tue, 1 Oct 2002 16:20:21 +0200 (CEST)
- Subject: bug with instruction set
hello,
I have an Athlon-4 (6.4.4 also knows as A9 rev by AMD), and when I chose
this procesor target (-march=athlon-4) gcc-3.2 uses SSE instructions which
aren't supported by Athlon-4.
Ans as far as I know, Athlon-4 isn't supposed to handle SSE (as a proof,
I got Illegal Instruction error, on cvtsi2ss ).
I found 2 temporary fix: use of athlon-tbird arch or -mno-sse flag. Which
is the best ?
Please ask if you need further/precise reporting
thanks,
Daimonos Tereutes