Re: c/3917: IA-64 assembler output shows erroneous cycle counting

[Guillermo Ballester Valor <gbv at ctv dot es>]

Hi:

wilson@gcc.gnu.org wrote:
> [snip]
>     The cycle counts indicate what the scheduler thinks the
>     hardware will do.  They will always be wrong to some
>     extent, because perfect emulation of the hardware
>     pipeline is difficult.  Also, current gcc infrastructure
>     does not have any easy way to describe pipelines as
>     complicated as the Itanium.  Major discrepancies should
>     be fixed though.
> 
>     I need a testcase to make sure that we are talking about
>     the same thing.  I have provided one of my own.
> 
>     double sub2 (double, double, double, double);
> 
>     double
>     sub (double w, double x, double y, double z, double a, double b, double c, double d)
>     {
>       return sub2 (a + b, c + d, a + b, c + d);
>     }
> 
>     With this testcase, I see that the 4 add instructions
>     get scheduled in 4 different cycles for no apparent
>     reason.
> 
	Yes, this is the problem I observed. Actually, in some cases, it
executes two FP instructions in a cycle, but scheduler didn't know, so
we can get an unpredicted dependence stall and slowdown the performance
(both integer and FP). 	

>     You are correct that there is a bug in itanium_split_issue.
>     It should allow 2 FP instructions per cycle.

	I though I was wrong (because some delay in reply). I see the gcc
package is complicate enough to make the things quickly. I was thinking
there was a limitation in gcc and it could not schedule two FP in a
cycle. Now, I think we can see a significative increase in performance
when this problem were resolved. 

> 
>     Your patch by the way is backwards.  You should always
>     do "diff oldfile newfile".
> 

Er, I guess you know I'm a newbe in this stuffs. Anyway I'm glad to help
gcc team. Hey, your compiler is the best in world! 

Regards.

Guillermo.

-- 
Guillermo Ballester Valor
gbv@ctv.es
Granada (Spain)