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Re: register renaming causes many ARM testsuite failures
On Wed, Jan 03, 2001 at 02:33:25PM -0800, Richard Henderson wrote:
> On Wed, Jan 03, 2001 at 05:30:46PM -0500, Michael Meissner wrote:
> > Ideally we should rerun the condition and predicates for register renaming
> > (especially the condition which is the only place where you can check operands
> > against each other).
>
> The problem with that is that prevents us from just collecting
> a chain of uses and renaming them all at once. We now have to
> do things piecemeal.
Well you could make a chain of insns for each register used, and go through
each insn after you changed it, if it hasn't already been run before. That
will add to the memory however.
The machine I'm working for instance has conditional compares, where the
condition register must use the same counterpart register of the comparison
register being set:
(define_insn "*cond_exec_cmpsi_cc"
[(cond_exec
(match_operator 0 "ccr_eqne_operator"
[(match_operand 1 "cr_operand" "C")
(const_int 0)])
(set (match_operand:CC 2 "icc_operand" "=t")
(compare:CC (match_operand:SI 3 "integer_register_operand" "d")
(match_operand:SI 4 "reg_or_0_operand" "dO"))))]
"reload_completed
&& REGNO (operands[1]) == REGNO (operands[2]) - ICC_FIRST + ICR_FIRST"
"ccmp %3, %z4, %1, %e0"
[(set_attr "length" "4")
(set_attr "type" "int")])
(the condition register is hand allocated by the IFCVT macros to satisfy this
condition).
The Power/PowerPC load/store string instructions require the registers to be
contiguous (presumably like the ARM).
--
Michael Meissner, Red Hat, Inc. (GCC group)
PMB 198, 174 Littleton Road #3, Westford, Massachusetts 01886, USA
Work: meissner@redhat.com phone: +1 978-486-9304
Non-work: meissner@spectacle-pond.org fax: +1 978-692-4482