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Re: ARM code generation bug with -O2...
- To: rearnsha at arm dot com
- Subject: Re: ARM code generation bug with -O2...
- From: Nick Clifton <nickc at cygnus dot com>
- Date: Mon, 3 Jul 2000 09:41:34 -0700
- CC: scottb at netwinder dot org, gcc-bugs at gcc dot gnu dot org, rearnsha at arm dot com
Hi Richard,
: This is OK, but incomplete. The tests should be the same as for post-inc
: ldr. That is, that the base isn't being loaded/stored and that if the
: increment is a register, it isn't the same register as the base. See the
: ldr peepholes in the same section for a template.
Ah, good point. OK, here is an extend version of the patch. This
version adds the check you mentioned above, plus it also adds similar
checks for the pre-inc peephole that follows after the post-inc
peepholes.
OK to apply ?
Cheers
Nick
2000-07-03 Nick Clifton <nickc@cygnus.com>
* config/arm/arm.md: Fix post increment and pre increment
peepholes so that they do not generate UNPREDICATBLE opcodes.
(ie ones where the increment clobbers the source/destination).
Index: gcc/config/arm/arm.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/arm/arm.md,v
retrieving revision 1.51
diff -p -r1.51 arm.md
*** arm.md 2000/06/03 10:44:59 1.51
--- arm.md 2000/07/03 16:36:47
***************
*** 7701,7715 ****
; It doesn't seem worth adding peepholes for anything but the most common
; cases since, unlike combine, the increment must immediately follow the load
; for this pattern to match.
! ; When loading we must watch to see that the base register isn't trampled by
! ; the load. In such cases this isn't a post-inc expression.
(define_peephole
[(set (mem:QI (match_operand:SI 0 "s_register_operand" "+r"))
(match_operand:QI 2 "s_register_operand" "r"))
(set (match_dup 0)
(plus:SI (match_dup 0) (match_operand:SI 1 "index_operand" "rJ")))]
! "TARGET_ARM"
"str%?b\\t%2, [%0], %1")
(define_peephole
--- 7701,7720 ----
; It doesn't seem worth adding peepholes for anything but the most common
; cases since, unlike combine, the increment must immediately follow the load
; for this pattern to match.
! ; We must watch to see that the source/destination register isn't also the
! ; same as the base address register, and that if the index is a register,
! ; that it is not the same as the base address register. In such cases the
! ; instruction that we would generate would have UNPREDICTABLE behaviour so
! ; we cannot use it.
(define_peephole
[(set (mem:QI (match_operand:SI 0 "s_register_operand" "+r"))
(match_operand:QI 2 "s_register_operand" "r"))
(set (match_dup 0)
(plus:SI (match_dup 0) (match_operand:SI 1 "index_operand" "rJ")))]
! "TARGET_ARM
! && (REGNO (operands[2]) != REGNO (operands[0]))
! && (GET_CODE (operands[1]) != REG || (REGNO (operands[1]) != REGNO (operands[0])))"
"str%?b\\t%2, [%0], %1")
(define_peephole
***************
*** 7717,7725 ****
(mem:QI (match_operand:SI 1 "s_register_operand" "+r")))
(set (match_dup 1)
(plus:SI (match_dup 1) (match_operand:SI 2 "index_operand" "rJ")))]
! "TARGET_ARM && REGNO(operands[0]) != REGNO(operands[1])
! && (GET_CODE (operands[2]) != REG
! || REGNO(operands[0]) != REGNO (operands[2]))"
"ldr%?b\\t%0, [%1], %2")
(define_peephole
--- 7722,7730 ----
(mem:QI (match_operand:SI 1 "s_register_operand" "+r")))
(set (match_dup 1)
(plus:SI (match_dup 1) (match_operand:SI 2 "index_operand" "rJ")))]
! "TARGET_ARM
! && REGNO(operands[0]) != REGNO(operands[1])
! && (GET_CODE (operands[2]) != REG || REGNO(operands[0]) != REGNO (operands[2]))"
"ldr%?b\\t%0, [%1], %2")
(define_peephole
***************
*** 7727,7733 ****
(match_operand:SI 2 "s_register_operand" "r"))
(set (match_dup 0)
(plus:SI (match_dup 0) (match_operand:SI 1 "index_operand" "rJ")))]
! "TARGET_ARM"
"str%?\\t%2, [%0], %1")
(define_peephole
--- 7732,7740 ----
(match_operand:SI 2 "s_register_operand" "r"))
(set (match_dup 0)
(plus:SI (match_dup 0) (match_operand:SI 1 "index_operand" "rJ")))]
! "TARGET_ARM
! && (REGNO (operands[2]) != REGNO (operands[0]))
! && (GET_CODE (operands[1]) != REG || (REGNO (operands[1]) != REGNO (operands[0])))"
"str%?\\t%2, [%0], %1")
(define_peephole
***************
*** 7739,7746 ****
&& (! BYTES_BIG_ENDIAN)
&& ! TARGET_MMU_TRAPS
&& REGNO(operands[0]) != REGNO(operands[1])
! && (GET_CODE (operands[2]) != REG
! || REGNO(operands[0]) != REGNO (operands[2]))"
"ldr%?\\t%0, [%1], %2\\t%@ loadhi")
(define_peephole
--- 7746,7752 ----
&& (! BYTES_BIG_ENDIAN)
&& ! TARGET_MMU_TRAPS
&& REGNO(operands[0]) != REGNO(operands[1])
! && (GET_CODE (operands[2]) != REG || REGNO(operands[0]) != REGNO (operands[2]))"
"ldr%?\\t%0, [%1], %2\\t%@ loadhi")
(define_peephole
***************
*** 7750,7757 ****
(plus:SI (match_dup 1) (match_operand:SI 2 "index_operand" "rJ")))]
"TARGET_ARM
&& REGNO(operands[0]) != REGNO(operands[1])
! && (GET_CODE (operands[2]) != REG
! || REGNO(operands[0]) != REGNO (operands[2]))"
"ldr%?\\t%0, [%1], %2")
(define_peephole
--- 7756,7762 ----
(plus:SI (match_dup 1) (match_operand:SI 2 "index_operand" "rJ")))]
"TARGET_ARM
&& REGNO(operands[0]) != REGNO(operands[1])
! && (GET_CODE (operands[2]) != REG || REGNO(operands[0]) != REGNO (operands[2]))"
"ldr%?\\t%0, [%1], %2")
(define_peephole
***************
*** 7759,7765 ****
(match_operand:SI 1 "index_operand" "rJ")))
(match_operand:QI 2 "s_register_operand" "r"))
(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))]
! "TARGET_ARM"
"str%?b\\t%2, [%0, %1]!")
(define_peephole
--- 7764,7772 ----
(match_operand:SI 1 "index_operand" "rJ")))
(match_operand:QI 2 "s_register_operand" "r"))
(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))]
! "TARGET_ARM
! && (REGNO (operands[2]) != REGNO (operands[0]))
! && (GET_CODE (operands[1]) != REG || (REGNO (operands[1]) != REGNO (operands[0])))"
"str%?b\\t%2, [%0, %1]!")
(define_peephole
***************
*** 7770,7776 ****
(match_operand:QI 3 "s_register_operand" "r"))
(set (match_dup 2) (plus:SI (match_op_dup 4 [(match_dup 0) (match_dup 1)])
(match_dup 2)))]
! "TARGET_ARM"
"str%?b\\t%3, [%2, %0%S4]!")
; This pattern is never tried by combine, so do it as a peephole
--- 7777,7785 ----
(match_operand:QI 3 "s_register_operand" "r"))
(set (match_dup 2) (plus:SI (match_op_dup 4 [(match_dup 0) (match_dup 1)])
(match_dup 2)))]
! "TARGET_ARM
! && (REGNO (operands[3]) != REGNO (operands[2]))
! && (REGNO (operands[0]) != REGNO (operands[2]))"
"str%?b\\t%3, [%2, %0%S4]!")
; This pattern is never tried by combine, so do it as a peephole