(set_attr "prefix" "maybe_evex")
(set_attr "mode" "<sseinsnmode>")])
+(define_insn_and_split "*avx_vec_concat<mode>_1"
+ [(set (match_operand:V_256_512 0 "register_operand")
+ (vec_concat:V_256_512
+ (vec_select:<ssehalfvecmode>
+ (unspec:V_256_512
+ [(match_operand:<ssehalfvecmode> 1 "nonimmediate_operand")]
+ UNSPEC_CAST)
+ (match_parallel 3 "avx_identity_operand"
+ [(match_operand 4 "const_int_operand")]))
+ (match_operand:<ssehalfvecmode> 2 "nonimm_or_0_operand")))]
+ "TARGET_AVX
+ && (operands[2] == CONST0_RTX (<ssehalfvecmode>mode)
+ || !MEM_P (operands[1]))
+ && ix86_pre_reload_split ()"
+ "#"
+ "&& 1"
+ [(set (match_dup 0) (vec_concat:V_256_512 (match_dup 1) (match_dup 2)))])
+
(define_insn "vcvtph2ps<mask_name>"
[(set (match_operand:V4SF 0 "register_operand" "=v")
(vec_select:V4SF