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2023-11-22 Maciej W. RozyckiRISC-V/testsuite: Add branchless cases for generic...
2023-11-22 Maciej W. RozyckiRISC-V/testsuite: Add branched cases for generic FP...
2023-11-22 Maciej W. RozyckiRISC-V: Avoid extraneous integer comparison for FP...
2023-11-22 Maciej W. RozyckiRISC-V: Provide FP conditional-branch instructions...
2023-11-22 Maciej W. RozyckiRISC-V: Also allow FP conditions in `riscv_expand_condi...
2023-11-22 Maciej W. RozyckiRISC-V: Only use SUBREG if applicable in `riscv_expand_...
2023-11-22 Maciej W. RozyckiRISC-V/testsuite: Add branchless cases for generic...
2023-11-22 Maciej W. RozyckiRISC-V/testsuite: Add branched cases for generic intege...
2023-11-22 Maciej W. RozyckiRISC-V: Add `addMODEcc' implementation for generic...
2023-11-22 Maciej W. RozyckiRISC-V/testsuite: Add branchless cases for generic...
2023-11-22 Maciej W. RozyckiRISC-V/testsuite: Add branched cases for generic intege...
2023-11-22 Maciej W. RozyckiRISC-V: Add `movMODEcc' implementation for generic...
2023-11-22 Maciej W. RozyckiRISC-V: Implement `riscv_emit_unary' helper
2023-11-22 Maciej W. RozyckiRISC-V/testsuite: Add branchless cases for T-Head non...
2023-11-22 Maciej W. RozyckiRISC-V/testsuite: Add branched cases for T-Head non...
2023-11-22 Maciej W. RozyckiRISC-V: Fold all the cond-move variants together
2023-11-22 Maciej W. RozyckiRISC-V: Also accept constants for T-Head cond-move...
2023-11-22 Maciej W. RozyckiRISC-V: Also accept constants for T-Head cond-move...
2023-11-22 Maciej W. RozyckiRISC-V/testsuite: Add branchless cases for equality...
2023-11-22 Maciej W. RozyckiRISC-V/testsuite: Add branched cases for equality cond...
2023-11-22 Maciej W. RozyckiRISC-V: Avoid extraneous EQ or NE operation in cond...
2023-11-22 Maciej W. RozyckiRISC-V/testsuite: Add branchless cases for GEU and...
2023-11-22 Maciej W. RozyckiRISC-V/testsuite: Add branched cases for GEU and LEU...
2023-11-22 Maciej W. RozyckiRISC-V: Also invert the cond-move condition for GEU...
2023-11-22 Maciej W. RozyckiRISC-V/testsuite: Add branchless cases for FP cond...
2023-11-22 Maciej W. RozyckiRISC-V/testsuite: Add branched cases for FP cond-move...
2023-11-22 Maciej W. RozyckiRISC-V/testsuite: Add branchless cases for integer...
2023-11-22 Maciej W. RozyckiRISC-V/testsuite: Add branched cases for integer cond...
2023-11-22 Maciej W. RozyckiRISC-V: Rework branch costing model for if-conversion
2023-11-22 Maciej W. RozyckiRISC-V: Simplify EQ vs NE selection in `riscv_expand_co...
2023-11-22 Maciej W. RozyckiRISC-V: Use `nullptr' in `riscv_expand_conditional_move'
2023-11-22 Maciej W. RozyckiRISC-V: Avoid repeated GET_MODE calls in `riscv_expand_...
2023-11-22 Maciej W. RozyckiRISC-V: Fix `mode' usage in `riscv_expand_conditional_move'
2023-11-22 Maciej W. RozyckiRISC-V: Sanitise NEED_EQ_NE_P case with `riscv_emit_int...
2023-11-22 Maciej W. RozyckiRISC-V: Reorder comment on SFB patterns
2023-11-22 Maciej W. RozyckiRISC-V/testsuite: Add cases for integer SFB cond-move...
2023-11-22 Maciej W. Rozyckitestsuite: Add cases for conditional-move and condition...
2023-11-22 Robin DappRISC-V: testsuite: Fix popcount test.
2023-11-22 Robin DappRISC-V: testsuite: Add rv64 requirement for bug-9 and...
2023-11-22 Robin DappRISC-V: testsuite: Do not set default arch for RVV.
2023-11-22 Patrick O'Neillgfortran: Rely on dg-do-what-default to avoid running...
2023-11-22 Juzhe-ZhongRISC-V: Disallow COSNT_VECTOR for DI on RV32
2023-11-22 Juzhe-ZhongRISC-V: Add missing dump check of pr112438.c
2023-11-22 Juzhe-ZhongRISC-V: Fix reduc_run-9.c test value check bug
2023-11-21 Jeff LawRevert "VECT: Support SLP MASK_LEN_GATHER_LOAD with...
2023-11-21 Andrew PinskiAdd support for vector conitional not
2023-11-21 Richard SandifordAllow md iterators to include other iterators
2023-11-21 Juzhe-ZhongRISC-V: Fix intermediate mode on slide1 instruction...
2023-11-21 Robin DappRISC-V: Disallow 64-bit indexed loads and stores for...
2023-11-21 Richard Sandifordmode-switching: Add a backprop hook
2023-11-21 Richard Sandifordmode-switching: Add a target-configurable confluence...
2023-11-21 Richard Sandifordmode-switching: Use 1-based edge aux fields
2023-11-21 Richard Sandifordmode-switching: Pass the set of live registers to the...
2023-11-21 Richard Sandifordmode-switching: Pass set of live registers to the neede...
2023-11-21 Richard Sandifordmode-switching: Allow targets to set the mode for EH...
2023-11-21 Richard Sandifordmode-switching: Tweak entry/exit handling
2023-11-21 Richard Sandifordmode-switching: Simplify recording of transparency
2023-11-21 Richard Sandifordmode-switching: Fix the mode passed to the emit hook
2023-11-21 Richard Sandifordmode-switching: Avoid quadractic list operation
2023-11-21 Richard Sandifordmode-switching: Add note problem
2023-11-21 Richard Sandifordmode-switching: Tweak the macro/hook documentation
2023-11-21 Richard Sandifordmode-switching: Remove unused bbnum field
2023-11-21 Robin Dappinternal-fn: Add VCOND_MASK_LEN.
2023-11-21 Juzhe-ZhongRISC-V Regression: Remove scalable compile option
2023-11-21 xuliRISC-V: Implement -mmemcpy-strategy= options[PR112537]
2023-11-21 Juzhe-ZhongRISC-V: Optimize constant AVL for LRA pattern
2023-11-21 Philipp Tomsich[committed] RISC-V: Infrastructure for instruction...
2023-11-21 Jeff Law[committed] Fix missing mode on a few unspec/unspec_vol...
2023-11-21 Juzhe-ZhongRISC-V: Fix bug of tuple move splitter
2023-11-21 Kito ChengRISC-V: Fix mismatched new delete for unique_ptr
2023-11-21 Juzhe-ZhongRISC-V: Refactor RVV iterators[NFC]
2023-11-21 Edwin LuRISC-V: Change unaligned fast/slow/avoid macros to...
2023-11-21 Kito ChengRISC-V: Implement target attribute
2023-11-21 Kito ChengRISC-V: Save/restore ra register correctly [PR112478]
2023-11-21 Juzhe-ZhongVECT: Clear LOOP_VINFO_USING_SELECT_VL_P when loop...
2023-11-21 Patrick O'NeillRISC-V: Fix ICE in non-canonical march parsing
2023-11-21 Juzhe-ZhongRISC-V: fix vsetvli pass testsuite failure [PR/112447]
2023-11-21 Vineet GuptaRISC-V: elide unnecessary sign extend when expanding...
2023-11-21 Juzhe-ZhongRISC-V: Support trailing vec_init optimization
2023-11-21 Pan LiRISC-V: Refine the mask generation for vec_init case 2
2023-11-21 Juzhe-ZhongRISC-V: Disallow RVV mode address for any load/store...
2023-11-21 Juzhe-ZhongRISC-V: Fix init-2.c assembly check
2023-11-21 Robin DappRISC-V: vsetvl: Refine REG_EQUAL equality.
2023-11-21 Juzhe-ZhongRISC-V: Adapt VLS init tests
2023-11-21 Juzhe-ZhongRISC-V: Optimize combine sequence by merge approach
2023-11-21 Pan LiRISC-V: Fix RVV dynamic frm tests failure
2023-11-21 Pan LiRISC-V: Support FP l/ll round and rint HF mode autovec
2023-11-21 Jeff LawRevert "[PATCH v2] In the pipeline, USE or CLOBBER...
2023-11-21 Jin Ma[PATCH v2] In the pipeline, USE or CLOBBER should delay...
2023-11-20 Juzhe-ZhongRISC-V: Add test for PR112469
2023-11-20 Maciej W. RozyckiRISC-V: Fix indentation of "length" attribute for branc...
2023-11-20 Patrick O'Neillg++: Rely on dg-do-what-default to avoid running pr1027...
2023-11-20 Vladimir N... [IRA]: Check autoinc and memory address after temporary...
2023-11-20 Juzhe-ZhongMiddle-end: Fix bug of induction variable vectorization...
2023-11-20 Juzhe-ZhongRISC-V: Add combine optimization by slideup for vec_ini...
2023-11-20 Robin DappRISC-V: testsuite: Fix 32-bit FAILs.
2023-11-20 Jin MaRISC-V: XTheadMemPair: Fix missing fcsr handling in...
2023-11-20 Juzhe-ZhongRISC-V: Robustify vec_init pattern[NFC]
2023-11-20 Pan LiRevert "RISC-V: Support vec_init for trailing same...
2023-11-20 Pan LiRISC-V: Support vec_init for trailing same element
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