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2023-09-18	Lehua Ding	RISC-V: Add missed cond autovec testcases	commit \| commitdiff \| tree
2023-09-18	xuli	RISC-V: Elimilate warning in class vcreate	commit \| commitdiff \| tree
2023-09-18	xuli	RISC-V: Add vcreate intrinsics for RVV tuple types	commit \| commitdiff \| tree
2023-09-18	Fei Gao	RISC-V: enable muti push and pop for Zcmp when shrink...	commit \| commitdiff \| tree
2023-09-18	Fei Gao	Allow targets to check shrink-wrap-separate enabled...	commit \| commitdiff \| tree
2023-09-18	Edwin Lu	RISC-V: Add Types to Un-Typed Thead Instructions	commit \| commitdiff \| tree
2023-09-18	Edwin Lu	RISC-V: Update Types for RISC-V Instructions	commit \| commitdiff \| tree
2023-09-18	Edwin Lu	RISC-V: Add Types to Un-Typed Zicond Instructions	commit \| commitdiff \| tree
2023-09-18	Edwin Lu	RISC-V: Add Types for Un-Typed zc Instructions	commit \| commitdiff \| tree
2023-09-18	Edwin Lu	RISC-V: Update Types for Vector Instructions	commit \| commitdiff \| tree
2023-09-18	Juzhe-Zhong	RISC-V: Enable RVV scalable vectorization by default...	commit \| commitdiff \| tree
2023-09-11	Juzhe-Zhong	RISC-V: Remove redundant functions	commit \| commitdiff \| tree
2023-09-11	Juzhe-Zhong	RISC-V: Use dominance analysis in global vsetvl elimination	commit \| commitdiff \| tree
2023-09-11	Juzhe-Zhong	RISC-V: Add VLS modes VEC_PERM support[PR111311]	commit \| commitdiff \| tree
2023-09-11	Juzhe-Zhong	RISC-V: Add missing VLS mask bool mode reg -> reg patterns	commit \| commitdiff \| tree
2023-09-11	Juzhe-Zhong	RISC-V: Expand fixed-vlmax/vls vector permutation in...	commit \| commitdiff \| tree
2023-09-11	Juzhe-Zhong	RISC-V: Avoid unnecessary slideup in compress pattern...	commit \| commitdiff \| tree
2023-09-11	Juzhe-Zhong	RISC-V: Fix dump FILE of VSETVL PASS[PR111311]	commit \| commitdiff \| tree
2023-09-11	Juzhe-Zhong	RISC-V: Fix VLS floating-point operations predicate	commit \| commitdiff \| tree
2023-09-11	Lehua Ding	Support folding min(poly,poly) to const	commit \| commitdiff \| tree
2023-09-11	Christoph Müllner	riscv: xtheadbb: Fix extendqi<SUPERQI> insn	commit \| commitdiff \| tree
2023-09-11	Christoph Müllner	riscv: thead: Fix mode attribute for extension patterns	commit \| commitdiff \| tree
2023-09-11	Christoph Müllner	riscv: bitmanip: Remove duplicate zero_extendhi<GPR...	commit \| commitdiff \| tree
2023-09-11	Juzhe-Zhong	RISC-V: Suppress bogus warning for VLS types	commit \| commitdiff \| tree
2023-09-11	Juzhe-Zhong	RISC-V: Fix incorrect nregs calculation for VLS modes	commit \| commitdiff \| tree
2023-09-11	Juzhe-Zhong	RISC-V: Add VLS mask modes mov patterns	commit \| commitdiff \| tree
2023-09-11	Juzhe-Zhong	RISC-V: Remove incorrect earliest vsetvl post optimizat...	commit \| commitdiff \| tree
2023-09-11	Tsukasa OI	RISC-V: Add support for 'XVentanaCondOps' reusing ...	commit \| commitdiff \| tree
2023-09-11	Juzhe-Zhong	RISC-V: Fix incorrect mode tieable which cause ICE...	commit \| commitdiff \| tree
2023-09-11	Juzhe-Zhong	RISC-V: Fix VSETVL PASS AVL/VL fetch bug[111295]	commit \| commitdiff \| tree
2023-09-11	Juzhe-Zhong	RISC-V: Remove unreasonable TARGET_64BIT for VLS modes...	commit \| commitdiff \| tree
2023-09-11	Pan Li	RISC-V: Fix incorrect folder for VRGATHERI16 test case	commit \| commitdiff \| tree
2023-09-11	Christoph Müllner	riscv: xtheadbb: Fix xtheadbb-li-rotr test for rv32	commit \| commitdiff \| tree
2023-09-11	Lehua Ding	RISC-V: Keep vlmax vector operators in simple form...	commit \| commitdiff \| tree
2023-09-11	Lehua Ding	RISC-V: Part-3: Output .variant_cc directive for vector...	commit \| commitdiff \| tree
2023-09-11	Lehua Ding	RISC-V: Part-2: Save/Restore vector registers which...	commit \| commitdiff \| tree
2023-09-11	Lehua Ding	RISC-V: Part-1: Select suitable vector registers for...	commit \| commitdiff \| tree
2023-09-11	Lehua Ding	RISC-V: Add conditional sqrt autovec pattern	commit \| commitdiff \| tree
2023-09-11	Tsukasa OI	RISC-V: typo: add closing paren to a comment	commit \| commitdiff \| tree
2023-09-11	Tsukasa OI	RISC-V: Fix Zicond ICE on large constants	commit \| commitdiff \| tree
2023-09-11	Christoph Müllner	riscv: Synthesize all 11-bit-rotate constants with...	commit \| commitdiff \| tree
2023-09-05	Jeff Law	RISC-V: Expose bswapsi for TARGET_64BIT	commit \| commitdiff \| tree
2023-09-05	Edwin Lu	RISC-V: Add Types to Un-Typed Risc-v Instructions	commit \| commitdiff \| tree
2023-09-05	Edwin Lu	RISC-V: Add Types to Un-Typed Pic Instructions	commit \| commitdiff \| tree
2023-09-05	Christoph Müllner	riscv: xtheadbb: Enable constant synthesis with th...	commit \| commitdiff \| tree
2023-09-05	Vineet Gupta	RISC-V: zicond: Fix opt2 pattern	commit \| commitdiff \| tree
2023-09-05	Kito Cheng	RISC-V: Emit .note.GNU-stack for non-linux target as...	commit \| commitdiff \| tree
2023-09-05	Pan Li	RISC-V: Support FP SGNJ autovec for VLS mode	commit \| commitdiff \| tree
2023-09-05	Juzhe-Zhong	RISC-V: Export functions as global extern preparing...	commit \| commitdiff \| tree
2023-09-05	Christoph Müllner	riscv: xtheadcondmov: Don't run tests with -Oz	commit \| commitdiff \| tree
2023-09-05	Juzhe-Zhong	RISC-V: Fix Dynamic LMUL compile option	commit \| commitdiff \| tree
2023-09-05	Pan Li	RISC-V: Support FP16 for RVV VRGATHEREI16 intrinsic	commit \| commitdiff \| tree
2023-09-05	Pan Li	RISC-V: Support FP MAX/MIN autovec for VLS mode	commit \| commitdiff \| tree
2023-09-05	Lehua Ding	RISC-V: Add conditional autovec convert(INT<->FP) patterns	commit \| commitdiff \| tree
2023-09-05	Lehua Ding	RISC-V: Add conditional autovec convert(FP<->FP) patterns	commit \| commitdiff \| tree
2023-09-05	Lehua Ding	RISC-V: Add conditional autovec convert(INT<->INT)...	commit \| commitdiff \| tree
2023-09-05	Lehua Ding	RISC-V: Adjust expand_cond_len_{unary,binop,op} api	commit \| commitdiff \| tree
2023-09-05	Juzhe-Zhong	RISC-V: Enable VECT_COMPARE_COSTS by default	commit \| commitdiff \| tree
2023-09-05	Robin Dapp	RISC-V: Add vec_extract for BI -> QI.	commit \| commitdiff \| tree
2023-09-05	Robin Dapp	testsuite/vect: Make match patterns more accurate.	commit \| commitdiff \| tree
2023-09-05	Juzhe-Zhong	RISC-V: Add dynamic LMUL compile option	commit \| commitdiff \| tree
2023-09-05	Pan Li	RISC-V: Support FP ADD/SUB/MUL/DIV autovec for VLS...	commit \| commitdiff \| tree
2023-09-05	Pan Li	RISC-V: Support rounding mode for VFNMADD/VFNMACC autovec	commit \| commitdiff \| tree
2023-09-05	Pan Li	RISC-V: Support rounding mode for VFNMSAC/VFNMSUB autovec	commit \| commitdiff \| tree
2023-09-05	Pan Li	RISC-V: Support rounding mode for VFMSAC/VFMSUB autovec	commit \| commitdiff \| tree
2023-09-05	Pan Li	RISC-V: Support rounding mode for VFMADD/VFMACC autovec	commit \| commitdiff \| tree
2023-09-05	Palmer Dabbelt	RISC-V: Add vector_scalar_shift_operand	commit \| commitdiff \| tree
2023-09-05	Juzhe-Zhong	RISC-V: Add Vector cost model framework for RVV	commit \| commitdiff \| tree
2023-09-05	Lehua Ding	RISC-V: Change vsetvl tail and mask policy to default...	commit \| commitdiff \| tree
2023-09-05	Lehua Ding	RISC-V: Refactor and clean emit_{vlmax,nonvlmax}_xxx...	commit \| commitdiff \| tree
2023-09-05	Lehua Ding	RISC-V: Fix vsetvl pass ICE	commit \| commitdiff \| tree
2023-09-05	Juzhe-Zhong	test: Add xfail into slp-reduc-7.c for RVV VLA vectoriz...	commit \| commitdiff \| tree
2023-09-05	Juzhe-Zhong	test: Adapt slp-26.c check for RVV	commit \| commitdiff \| tree
2023-09-05	Juzhe-Zhong	RISC-V: Remove movmisalign pattern for VLA modes	commit \| commitdiff \| tree
2023-09-05	Juzhe-Zhong	test: Fix XPASS of RVV	commit \| commitdiff \| tree
2023-09-05	Juzhe-Zhong	test: Add xfail for riscv_vector	commit \| commitdiff \| tree
2023-09-05	Die Li	RISC-V: support cm.mva01s cm.mvsa01 in zcmp	commit \| commitdiff \| tree
2023-09-05	Fei Gao	RISC-V: support cm.popretz in zcmp	commit \| commitdiff \| tree
2023-09-05	Fei Gao	RISC-V: support cm.push cm.pop cm.popret in zcmp	commit \| commitdiff \| tree
2023-09-05	Juzhe-Zhong	middle-end: Apply MASK_LEN_LOAD_LANES/MASK_LEN_STORE_LA...	commit \| commitdiff \| tree
2023-09-05	Tsukasa OI	RISC-V: Make arch-24.c to test "success" case	commit \| commitdiff \| tree
2023-09-05	Juzhe-Zhong	RISC-V: Make sure we get VL REG operand for VLMAX vsetvl	commit \| commitdiff \| tree
2023-09-05	Juzhe-Zhong	RISC-V: Enable movmisalign for VLS modes	commit \| commitdiff \| tree
2023-09-05	Philipp Tomsich	RISC-V: Use splitter to generate zicond in another...	commit \| commitdiff \| tree
2023-09-05	Jin Ma	RISC-V: Added zvfh support for zfa extensions.	commit \| commitdiff \| tree
2023-09-05	Edwin Lu	RISC-V: generate builtin macro for compilation with...	commit \| commitdiff \| tree
2023-09-05	Edwin Lu	RISC-V: Add Types to Un-Typed Vector Instructions	commit \| commitdiff \| tree
2023-09-05	Pan Li	RISC-V: Fix one ICE for vect test vect-multitypes-5	commit \| commitdiff \| tree
2023-09-05	Tsukasa OI	RISC-V: Add stub support for existing extensions (unpri...	commit \| commitdiff \| tree
2023-09-05	Tsukasa OI	RISC-V: Add stub support for existing extensions (vendor)	commit \| commitdiff \| tree
2023-09-05	Tsukasa OI	RISC-V: Add stub support for existing extensions (privi...	commit \| commitdiff \| tree
2023-09-05	Tsukasa OI	RISC-V: Make PR 102957 tests more comprehensive	commit \| commitdiff \| tree
2023-09-05	Lehua Ding	RISC-V: Refactor and clean expand_cond_len_{unop,binop...	commit \| commitdiff \| tree
2023-09-05	Juzhe-Zhong	vect test: Remove xfail for riscv	commit \| commitdiff \| tree
2023-09-05	Juzhe-Zhong	RISC-V: Fix ASM check of vlmax_switch_vtype-16.c	commit \| commitdiff \| tree
2023-09-05	Juzhe-Zhong	RISC-V: Fix AVL/VL get ICE[VSETVL PASS]	commit \| commitdiff \| tree
2023-09-05	Lehua Ding	RISC-V: Fix error combine of pred_mov pattern	commit \| commitdiff \| tree
2023-09-05	Tsukasa OI	RISC-V: Fix documentation of __builtin_riscv_pause	commit \| commitdiff \| tree
2023-09-05	Tsukasa OI	RISC-V: __builtin_riscv_pause for all environment	commit \| commitdiff \| tree
2023-09-05	Juzhe-Zhong	RISC-V: Fix uninitialized probability for GIMPLE IR...	commit \| commitdiff \| tree
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