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2023-01-30	Ju-Zhe Zhong	RISC-V: Add indexed loads/stores constraints testcases	commit \| commitdiff \| tree
2023-01-30	Ju-Zhe Zhong	RISC-V: Add VSETVL testcases for indexed loads/stores.	commit \| commitdiff \| tree
2023-01-30	Ju-Zhe Zhong	RISC-V: Add indexed loads/stores C/C++ intrinsic support	commit \| commitdiff \| tree
2023-01-28	Ju-Zhe Zhong	RISC-V: Add vlse/vsse C/C++ intrinsic testcases	commit \| commitdiff \| tree
2023-01-28	Ju-Zhe Zhong	RISC-V: Add vlse/vsse intrinsics support	commit \| commitdiff \| tree
2023-01-28	Ju-Zhe Zhong	RISC-V: Remove redundant attributes [NFC]	commit \| commitdiff \| tree
2023-01-27	Ju-Zhe Zhong	RISC-V: Fix testcases check.	commit \| commitdiff \| tree
2023-01-27	Ju-Zhe Zhong	RISC-V: Add vle/vse C++ overloaded API intrinsic testcases	commit \| commitdiff \| tree
2023-01-27	Ju-Zhe Zhong	RISC-V: Fix vop_m overloaded C++ API name.	commit \| commitdiff \| tree
2023-01-27	Ju-Zhe Zhong	RISC-V: Add vse.v C API intrinsics testcases	commit \| commitdiff \| tree
2023-01-27	Ju-Zhe Zhong	RISC-V: Add vle.v C API intrinsics testcases	commit \| commitdiff \| tree
2023-01-27	Ju-Zhe Zhong	RISC-V: Add vlm/vsm C/C++ API intrinsics support	commit \| commitdiff \| tree
2023-01-27	Ju-Zhe Zhong	RISC-V: Finalize testcases for final version VSETVL...	commit \| commitdiff \| tree
2023-01-27	Ju-Zhe Zhong	RISC-V: Finalize VSETVL PASS implementation	commit \| commitdiff \| tree
2023-01-27	Ju-Zhe Zhong	RISC-V: Fix bug of before_p function	commit \| commitdiff \| tree
2023-01-27	Ju-Zhe Zhong	RISC-V: Refine function args of some functions.	commit \| commitdiff \| tree
2023-01-27	Ju-Zhe Zhong	RISC-V: Fix pred_mov constraint for vle.v	commit \| commitdiff \| tree
2023-01-27	Ju-Zhe Zhong	RISC-V: Add TARGET_MIN_VLEN > 32 into iterators of...	commit \| commitdiff \| tree
2023-01-27	Ju-Zhe Zhong	RISC-V: Change parse_insn into public for future use.	commit \| commitdiff \| tree
2023-01-27	Ju-Zhe Zhong	RISC-V: Reorder VSETVL pass location	commit \| commitdiff \| tree
2023-01-27	Ju-Zhe Zhong	RISC-V: Change VSETVL PASS always call split_all_insns	commit \| commitdiff \| tree
2023-01-27	Ju-Zhe Zhong	RISC-V: Fix incorrect attributes of vsetvl instructions...	commit \| commitdiff \| tree
2023-01-26	Ju-Zhe Zhong	RISC-V: Add testcases for AVL=REG support	commit \| commitdiff \| tree
2023-01-26	Ju-Zhe Zhong	RISC-V: Add testcases for IMM (0 ~ 31) AVL	commit \| commitdiff \| tree
2023-01-26	Ju-Zhe Zhong	RISC-V: Fix bugs of supporting AVL=REG (single-real...	commit \| commitdiff \| tree
2023-01-26	Ju-Zhe Zhong	RISC-V: Add probability model of each block to prevent...	commit \| commitdiff \| tree
2023-01-26	Ju-Zhe Zhong	RISC-V: Remove dirty_pat since it is redundant	commit \| commitdiff \| tree
2023-01-26	Ju-Zhe Zhong	RISC-V: Rename insn into rinsn for rtx_insn * [NFC]	commit \| commitdiff \| tree
2023-01-26	Ju-Zhe Zhong	RISC-V: Refine codes in backward fusion [NFC]	commit \| commitdiff \| tree
2023-01-26	Ju-Zhe Zhong	RISC-V: Avoid redundant flow in forward fusion	commit \| commitdiff \| tree
2023-01-26	Ju-Zhe Zhong	RISC-V: Cleanup the codes of bitmap create and free...	commit \| commitdiff \| tree
2023-01-26	Ju-Zhe Zhong	RISC-V: Refine Phase 3 of VSETVL PASS	commit \| commitdiff \| tree
2023-01-26	Ju-Zhe Zhong	RISC-V: Fix bugs of available condition.	commit \| commitdiff \| tree
2023-01-26	Ju-Zhe Zhong	RISC-V: Simplify codes of changing vsetvl instruction	commit \| commitdiff \| tree
2023-01-26	Ju-Zhe Zhong	RISC-V: Fix backward_propagate_worthwhile_p	commit \| commitdiff \| tree
2023-01-26	Ju-Zhe Zhong	RISC-V: Fix wrong in_group flag in validate_change...	commit \| commitdiff \| tree
2023-01-26	Ju-Zhe Zhong	RISC-V: Fix bugs for refine vsetvl a5, zero into vsetvl...	commit \| commitdiff \| tree
2023-01-26	Ju-Zhe Zhong	RISC-V: Fix vsetivli instruction asm for IMM AVL	commit \| commitdiff \| tree
2023-01-26	Ju-Zhe Zhong	RISC-V: Fix inferior codegen for vse intrinsics.	commit \| commitdiff \| tree
2023-01-26	Ju-Zhe Zhong	RISC-V: Fix pointer tree type for store pointer.	commit \| commitdiff \| tree
2022-12-27	Ju-Zhe Zhong	RISC-V: Fix ICE of visiting non-existing block in CFG.	commit \| commitdiff \| tree
2022-12-27	Ju-Zhe Zhong	RISC-V: Fix ICE for avl_info deprecated copy and pp_print...	commit \| commitdiff \| tree
2022-12-23	Ju-Zhe Zhong	RISC-V: Fix vle constraints	commit \| commitdiff \| tree
2022-12-23	Ju-Zhe Zhong	RISC-V: Support vle.v/vse.v intrinsics	commit \| commitdiff \| tree
2022-12-23	Ju-Zhe Zhong	RISC-V: Update vsetvl/vsetvlmax intrinsics to the latest...	commit \| commitdiff \| tree
2022-12-23	Ju-Zhe Zhong	RISC-V: Remove side effects of vsetvl pattern in RTL.	commit \| commitdiff \| tree
2022-12-23	Ju-Zhe Zhong	RISC-V: Remove side effects of vsetvl/vsetvlmax intriniscs...	commit \| commitdiff \| tree
2022-12-23	Ju-Zhe Zhong	RISC-V: Fix incorrect annotation	commit \| commitdiff \| tree
2022-12-23	Ju-Zhe Zhong	RISC-V: Fix muti-line condition format	commit \| commitdiff \| tree
2022-12-19	Ju-Zhe Zhong	RISC-V: Remove unit-stride store from ta attribute	commit \| commitdiff \| tree
2022-12-19	Ju-Zhe Zhong	RISC-V: Add testcases for VSETVL PASS 5	commit \| commitdiff \| tree
2022-12-19	Ju-Zhe Zhong	RISC-V: Add testcases for VSETVL PASS 4	commit \| commitdiff \| tree
2022-12-19	Ju-Zhe Zhong	RISC-V: Add testcases for VSETVL PASS 3	commit \| commitdiff \| tree
2022-12-19	Ju-Zhe Zhong	RISC-V: Add testcases for VSETVL PASS 2	commit \| commitdiff \| tree
2022-12-19	Ju-Zhe Zhong	RISC-V: Add testcases for VSETVL PASS	commit \| commitdiff \| tree
2022-12-19	Ju-Zhe Zhong	RISC-V: Support VSETVL PASS for RVV support	commit \| commitdiff \| tree
2022-12-19	Ju-Zhe Zhong	RISC-V: Fix RVV machine mode attribute configuration	commit \| commitdiff \| tree
2022-12-19	Ju-Zhe Zhong	RISC-V: Change vlmul printing rule	commit \| commitdiff \| tree
2022-12-01	Ju-Zhe Zhong	RISC-V: Remove tail && mask policy operand for vmclr...	commit \| commitdiff \| tree
2022-12-01	Ju-Zhe Zhong	RISC-V: Add attributes for VSETVL PASS	commit \| commitdiff \| tree
2022-12-01	Ju-Zhe Zhong	RISC-V: Add duplicate vector support.	commit \| commitdiff \| tree
2022-11-11	Ju-Zhe Zhong	RISC-V: Add RVV registers register spilling	commit \| commitdiff \| tree
2022-10-31	Ju-Zhe Zhong	RISC-V: Change constexpr back to CONSTEXPR	commit \| commitdiff \| tree
2022-10-26	Ju-Zhe Zhong	RISC-V: Fix epilogue generation for barrier. ...patch/20220817071950.271762-1-juzhe.zhong@rivai.ai/	commit \| commitdiff \| tree
2022-10-26	Ju-Zhe Zhong	RISC-V: ADJUST_NUNITS according to -march.	commit \| commitdiff \| tree
2022-10-26	Ju-Zhe Zhong	RISC-V: Support load/store in mov<mode> pattern for...	commit \| commitdiff \| tree
2022-10-26	Ju-Zhe Zhong	RISC-V: Adjust table indentation in commnet for riscv...	commit \| commitdiff \| tree
2022-10-24	Ju-Zhe Zhong	RISC-V: Support (set (mem) (const_poly_int))	commit \| commitdiff \| tree
2022-10-24	Ju-Zhe Zhong	RISC-V: Replace CONSTEXPR with constexpr	commit \| commitdiff \| tree
2022-10-24	Ju-Zhe Zhong	RISC-V: Remove unused TI/TF vector modes.	commit \| commitdiff \| tree
2022-10-24	Ju-Zhe Zhong	RISC-V: Fix REG_CLASS_CONTENTS.	commit \| commitdiff \| tree
2022-10-21	Ju-Zhe Zhong	RISC-V: Add RVV vsetvl/vsetvlmax intrinsics and tests.	commit \| commitdiff \| tree
2022-10-21	Ju-Zhe Zhong	RISC-V: Add RVV intrinsic basic framework.	commit \| commitdiff \| tree
2022-10-17	Ju-Zhe Zhong	RISC-V: Fix format[NFC]	commit \| commitdiff \| tree
2022-10-17	Ju-Zhe Zhong	RISC-V: Reorganize mangle_builtin_type.[NFC]	commit \| commitdiff \| tree
2022-10-12	Ju-Zhe Zhong	RISC-V: Remove TUPLE size macro define. [NFC]	commit \| commitdiff \| tree
2022-10-12	Ju-Zhe Zhong	RISC-V: Apply clang-format for riscv-vector-builtins...	commit \| commitdiff \| tree
2022-10-12	Ju-Zhe Zhong	RISC-V: Refine register_builtin_types function. [NFC]	commit \| commitdiff \| tree
2022-10-12	Ju-Zhe Zhong	RISC-V: Move function place to make it looks better...	commit \| commitdiff \| tree
2022-10-11	Ju-Zhe Zhong	RISC-V: move struct vector_type_info from .h to ...	commit \| commitdiff \| tree
2022-10-11	Ju-Zhe Zhong	RISC-V: Add missing vsetvl instruction type.	commit \| commitdiff \| tree
2022-10-05	Ju-Zhe Zhong	RISC-V: Introduce RVV header to enable builtin types	commit \| commitdiff \| tree
2022-09-28	Ju-Zhe Zhong	RISC-V: Add ABI-defined RVV types.	commit \| commitdiff \| tree
2022-09-23	zhongjuzhe	RISC-V: Add RVV machine modes.	commit \| commitdiff \| tree
2022-09-23	zhongjuzhe	RISC-V: Support poly move manipulation and selftests.	commit \| commitdiff \| tree
2022-09-01	zhongjuzhe	RISC-V: Add vector registers in TARGET_CONDITIONAL_REGISTER_...	commit \| commitdiff \| tree
2022-09-01	zhongjuzhe	RISC-V: Add csrr vlenb instruction.	commit \| commitdiff \| tree
2022-09-01	zhongjuzhe	RISC-V: Add RVV constraints.	commit \| commitdiff \| tree
2022-09-01	zhongjuzhe	RISC-V: Fix comment in riscv.h	commit \| commitdiff \| tree
2022-09-01	zhongjuzhe	RISC-V: Fix riscv_vector_chunks configuration according...	commit \| commitdiff \| tree
2022-08-31	zhongjuzhe	middle-end: Fix unexpected warnings for RISC-V port.	commit \| commitdiff \| tree
2022-08-29	zhongjuzhe	RISC-V: Add RVV registers	commit \| commitdiff \| tree
2022-08-29	zhongjuzhe	RISC-V: Add RVV instructions classification	commit \| commitdiff \| tree
2022-08-22	zhongjuzhe	middle-end: Fix issue of poly_uint16 (1, 1) in self...	commit \| commitdiff \| tree
2022-08-18	zhongjuzhe	RISC-V: Add runtime invariant support	commit \| commitdiff \| tree

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