From f3e368a722e550ff32bc76d6da555e824e07c4ca Mon Sep 17 00:00:00 2001
From: "Maciej W. Rozycki" <macro@embecosm.com>
Date: Wed, 22 Nov 2023 01:18:26 +0000
Subject: [PATCH] RISC-V/testsuite: Add branched cases for GEU and LEU
 cond-move operations

Verify, for Ventana and Zicond targets and the GEU and LEU
conditional-move operations, that if-conversion does *not* trigger at
`-mbranch-cost=3' setting, which makes original branched code sequences
cheaper than their branchless equivalents if-conversion would emit.

	gcc/testsuite/
	* gcc.target/riscv/movdibgtu-ventana.c: New test.
	* gcc.target/riscv/movdibgtu-zicond.c: New test.
	* gcc.target/riscv/movdibltu-ventana.c: New test.
	* gcc.target/riscv/movdibltu-zicond.c: New test.
	* gcc.target/riscv/movsibgtu-ventana.c: New test.
	* gcc.target/riscv/movsibgtu-zicond.c: New test.
	* gcc.target/riscv/movsibltu-ventana.c: New test.
	* gcc.target/riscv/movsibltu-zicond.c: New test.

(cherry picked from commit cfa6536f29d19300d0687f4c9ae07800278ad31f)
---
 .../gcc.target/riscv/movdibgtu-ventana.c      | 28 +++++++++++++++++++
 .../gcc.target/riscv/movdibgtu-zicond.c       | 28 +++++++++++++++++++
 .../gcc.target/riscv/movdibltu-ventana.c      | 28 +++++++++++++++++++
 .../gcc.target/riscv/movdibltu-zicond.c       | 28 +++++++++++++++++++
 .../gcc.target/riscv/movsibgtu-ventana.c      | 28 +++++++++++++++++++
 .../gcc.target/riscv/movsibgtu-zicond.c       | 28 +++++++++++++++++++
 .../gcc.target/riscv/movsibltu-ventana.c      | 28 +++++++++++++++++++
 .../gcc.target/riscv/movsibltu-zicond.c       | 28 +++++++++++++++++++
 8 files changed, 224 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/movdibgtu-ventana.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/movdibgtu-zicond.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/movdibltu-ventana.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/movdibltu-zicond.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/movsibgtu-ventana.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/movsibgtu-zicond.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/movsibltu-ventana.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/movsibltu-zicond.c

diff --git a/gcc/testsuite/gcc.target/riscv/movdibgtu-ventana.c b/gcc/testsuite/gcc.target/riscv/movdibgtu-ventana.c
new file mode 100644
index 000000000000..ea4548d81b04
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movdibgtu-ventana.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */
+
+typedef unsigned int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdigtu (int_t w, int_t x, int_t y, int_t z)
+{
+  return w > x ? y : z;
+}
+
+/* Expect branched assembly like:
+
+	bleu	a0,a1,.L2
+	mv	a3,a2
+.L2:
+	mv	a0,a3
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:bgeu|bgtu|bleu|bltu)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */
+/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */
+/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movdibgtu-zicond.c b/gcc/testsuite/gcc.target/riscv/movdibgtu-zicond.c
new file mode 100644
index 000000000000..19198f25f341
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movdibgtu-zicond.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */
+
+typedef unsigned int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdigtu (int_t w, int_t x, int_t y, int_t z)
+{
+  return w > x ? y : z;
+}
+
+/* Expect branched assembly like:
+
+	bleu	a0,a1,.L2
+	mv	a3,a2
+.L2:
+	mv	a0,a3
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:bgeu|bgtu|bleu|bltu)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */
+/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */
+/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movdibltu-ventana.c b/gcc/testsuite/gcc.target/riscv/movdibltu-ventana.c
new file mode 100644
index 000000000000..c92a49404779
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movdibltu-ventana.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */
+
+typedef unsigned int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdiltu (int_t w, int_t x, int_t y, int_t z)
+{
+  return w < x ? y : z;
+}
+
+/* Expect branched assembly like:
+
+	bgeu	a0,a1,.L2
+	mv	a3,a2
+.L2:
+	mv	a0,a3
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:bgeu|bgtu|bleu|bltu)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */
+/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */
+/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movdibltu-zicond.c b/gcc/testsuite/gcc.target/riscv/movdibltu-zicond.c
new file mode 100644
index 000000000000..68bdccf160c1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movdibltu-zicond.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */
+
+typedef unsigned int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdiltu (int_t w, int_t x, int_t y, int_t z)
+{
+  return w < x ? y : z;
+}
+
+/* Expect branched assembly like:
+
+	bgeu	a0,a1,.L2
+	mv	a3,a2
+.L2:
+	mv	a0,a3
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:bgeu|bgtu|bleu|bltu)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */
+/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */
+/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movsibgtu-ventana.c b/gcc/testsuite/gcc.target/riscv/movsibgtu-ventana.c
new file mode 100644
index 000000000000..0716ba8f8606
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movsibgtu-ventana.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */
+
+typedef unsigned int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsigtu (int_t w, int_t x, int_t y, int_t z)
+{
+  return w > x ? y : z;
+}
+
+/* Expect branched assembly like:
+
+	bleu	a0,a1,.L2
+	mv	a3,a2
+.L2:
+	mv	a0,a3
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:bgeu|bgtu|bleu|bltu)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */
+/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */
+/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movsibgtu-zicond.c b/gcc/testsuite/gcc.target/riscv/movsibgtu-zicond.c
new file mode 100644
index 000000000000..a8018cd066d9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movsibgtu-zicond.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" { target { rv32 } } } */
+
+typedef unsigned int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsigtu (int_t w, int_t x, int_t y, int_t z)
+{
+  return w > x ? y : z;
+}
+
+/* Expect branched assembly like:
+
+	bleu	a0,a1,.L2
+	mv	a3,a2
+.L2:
+	mv	a0,a3
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:bgeu|bgtu|bleu|bltu)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */
+/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */
+/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movsibltu-ventana.c b/gcc/testsuite/gcc.target/riscv/movsibltu-ventana.c
new file mode 100644
index 000000000000..8f45f02c087b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movsibltu-ventana.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */
+
+typedef unsigned int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsiltu (int_t w, int_t x, int_t y, int_t z)
+{
+  return w < x ? y : z;
+}
+
+/* Expect branched assembly like:
+
+	bgeu	a0,a1,.L2
+	mv	a3,a2
+.L2:
+	mv	a0,a3
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:bgeu|bgtu|bleu|bltu)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */
+/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */
+/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movsibltu-zicond.c b/gcc/testsuite/gcc.target/riscv/movsibltu-zicond.c
new file mode 100644
index 000000000000..0abb111271d8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movsibltu-zicond.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" { target { rv32 } } } */
+
+typedef unsigned int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsiltu (int_t w, int_t x, int_t y, int_t z)
+{
+  return w < x ? y : z;
+}
+
+/* Expect branched assembly like:
+
+	bgeu	a0,a1,.L2
+	mv	a3,a2
+.L2:
+	mv	a0,a3
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:bgeu|bgtu|bleu|bltu)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */
+/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */
+/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
-- 
2.43.5