From d16093fdff612ff4bac76f70a66afa5a320e4f04 Mon Sep 17 00:00:00 2001 From: Uros Bizjak Date: Wed, 31 Aug 2005 19:27:53 +0200 Subject: [PATCH] re PR target/23570 (internal compiler error: in merge_assigned_reloads, at reload1.c:6091) PR target/23570 * config/i386/sse.md (*sse_concatv2sf): Change operand 2 constraint to "reg_or_0_operand". (sse2_loadld): Change operand 1 constraint to "reg_or_0_operand". From-SVN: r103690 --- gcc/ChangeLog | 7 ++ gcc/config/i386/sse.md | 4 +- gcc/testsuite/gcc.target/i386/pr23570.c | 92 +++++++++++++++++++++++++ 3 files changed, 101 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr23570.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 556581599ae5..481e4f70e295 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2005-08-31 Uros Bizjak + + PR target/23570 + * config/i386/sse.md (*sse_concatv2sf): Change operand 2 constraint + to "reg_or_0_operand". + (sse2_loadld): Change operand 1 constraint to "reg_or_0_operand". + 2005-08-31 Dale Johannesen * loop-iv.c (iv_number_of_iterations): Fix overflow check for diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 4bd10400473d..95cb79757e8e 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -1230,7 +1230,7 @@ [(set (match_operand:V2SF 0 "register_operand" "=x,x,*y,*y") (vec_concat:V2SF (match_operand:SF 1 "nonimmediate_operand" " 0,m, 0, m") - (match_operand:SF 2 "vector_move_operand" " x,C,*y, C")))] + (match_operand:SF 2 "reg_or_0_operand" " x,C,*y, C")))] "TARGET_SSE" "@ unpcklps\t{%2, %0|%0, %2} @@ -3374,7 +3374,7 @@ (vec_merge:V4SI (vec_duplicate:V4SI (match_operand:SI 2 "nonimmediate_operand" "mr,m,x")) - (match_operand:V4SI 1 "vector_move_operand" " C,C,0") + (match_operand:V4SI 1 "reg_or_0_operand" " C,C,0") (const_int 1)))] "TARGET_SSE" "@ diff --git a/gcc/testsuite/gcc.target/i386/pr23570.c b/gcc/testsuite/gcc.target/i386/pr23570.c new file mode 100644 index 000000000000..1542663fa22c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr23570.c @@ -0,0 +1,92 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2" } */ + +typedef float __v4sf __attribute__ ((__vector_size__ (16))); +typedef float __m128 __attribute__ ((__vector_size__ (16))); +typedef long long __v2di __attribute__ ((__vector_size__ (16))); + +static __inline __m128 +_mm_cmpeq_ps (__m128 __A, __m128 __B) +{ + return (__m128) __builtin_ia32_cmpeqps ((__v4sf)__A, (__v4sf)__B); +} + +static __inline __m128 +_mm_setr_ps (float __Z, float __Y, float __X, float __W) +{ + return __extension__ (__m128)(__v4sf){__Z, __Y, __X, __W }; +} + +static __inline __m128 +_mm_and_si128 (__m128 __A, __m128 __B) +{ + return (__m128)__builtin_ia32_pand128 ((__v2di)__A, (__v2di)__B); +} + +static __inline __m128 +_mm_or_si128 (__m128 __A, __m128 __B) +{ + return (__m128)__builtin_ia32_por128 ((__v2di)__A, (__v2di)__B); +} + +typedef union +{ + __m128 xmmi; + int si[4]; +} +__attribute__ ((aligned (16))) um128; + +um128 u; + +static inline int +sse_max_abs_indexf (float *v, int step, int n) +{ + __m128 m1, mm; + __m128 mim, mi, msk; + um128 u, ui; + int n4, step2, step3; + mm = __builtin_ia32_andps ((__m128) (__v4sf) + { 0.0, v[step], v[step2], v[step3] } + , u.xmmi); + if (n4) + { + int i; + for (i = 0; i < n4; ++i); + msk = (__m128) _mm_cmpeq_ps (m1, mm); + mim = _mm_or_si128 (_mm_and_si128 (msk, mi), mim); + } + ui.xmmi = (__m128) mim; + return ui.si[n]; +} + +static void +sse_swap_rowf (float *r1, float *r2, int n) +{ + int n4 = (n / 4) * 4; + float *r14end = r1 + n4; + while (r1 < r14end) + { + *r1 = *r2; + r1++; + } +} + +void +ludcompf (float *m, int nw, int *prow, int n) +{ + int i, s = 0; + float *pm; + for (i = 0, pm = m; i < n - 1; ++i, pm += nw) + { + int vi = sse_max_abs_indexf (pm + i, nw, n - i); + float *pt; + int j; + if (vi != 0) + { + sse_swap_rowf (pm, pm + vi * nw, nw); + swap_index (prow, i, i + vi); + } + for (j = i + 1, pt = pm + nw; j < n; ++j, pt += nw) + sse_add_rowf (pt + i + 1, pm + i + 1, -1.0, n - i - 1); + } +} -- 2.43.5