From 9a9286af3ce28d8231fb27e5f345d9f89f4332d7 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Mon, 13 Dec 2004 02:27:46 -0800 Subject: [PATCH] Makefile.in (insn-preds.o): Depend on REGS_H. * Makefile.in (insn-preds.o): Depend on REGS_H. * genpreds.c (write_insn_preds_c): Include regs.h. * config/i386/predicates.md (index_register_operand): Use REG_OK_FOR_INDEX_STRICT_P and REG_OK_FOR_INDEX_NONSTRICT_P. * config/i386/i386.h (REG_CLASS_FROM_LETTER): Add 'l'. * config/i386/i386.md (lea_general_1, lea_general_1_zext, lea_general_2, lea_general_2_zext, lea_general_3, lea_general_3_zext, adddi_1_rex64, addsi_1, addsi_1_zext, addhi_1_lea, addqi_1_lea, ashldi3_1_rex64, ashlsi3_1, ashlsi3_1_zext, ashlhi3_1_lea, ashlqi3_1_lea): Use 'l' for index register operand. (ashldi3_1_rex64 splitter): Use index_register_operand. (ashlsi3_1 splitter): Be more careful with modes. From-SVN: r92080 --- gcc/ChangeLog | 16 ++++++++++++ gcc/Makefile.in | 3 ++- gcc/config/i386/i386.h | 9 ++++++- gcc/config/i386/i386.md | 49 ++++++++++++++++++++--------------- gcc/config/i386/predicates.md | 9 +++---- gcc/genpreds.c | 3 ++- 6 files changed, 60 insertions(+), 29 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6425f0b00161..191f2275950b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,19 @@ +2004-12-13 Richard Henderson + + * Makefile.in (insn-preds.o): Depend on REGS_H. + * genpreds.c (write_insn_preds_c): Include regs.h. + * config/i386/predicates.md (index_register_operand): Use + REG_OK_FOR_INDEX_STRICT_P and REG_OK_FOR_INDEX_NONSTRICT_P. + + * config/i386/i386.h (REG_CLASS_FROM_LETTER): Add 'l'. + * config/i386/i386.md (lea_general_1, lea_general_1_zext, + lea_general_2, lea_general_2_zext, lea_general_3, lea_general_3_zext, + adddi_1_rex64, addsi_1, addsi_1_zext, addhi_1_lea, addqi_1_lea, + ashldi3_1_rex64, ashlsi3_1, ashlsi3_1_zext, ashlhi3_1_lea, + ashlqi3_1_lea): Use 'l' for index register operand. + (ashldi3_1_rex64 splitter): Use index_register_operand. + (ashlsi3_1 splitter): Be more careful with modes. + 2004-12-13 Danny Smith PR target/18459 diff --git a/gcc/Makefile.in b/gcc/Makefile.in index 15490066989a..b0f779c8cc4b 100644 --- a/gcc/Makefile.in +++ b/gcc/Makefile.in @@ -2397,7 +2397,8 @@ s-preds: $(md_file) build/genpreds$(build_exeext) insn-preds.o : insn-preds.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \ $(RTL_H) $(TREE_H) insn-config.h $(RECOG_H) real.h output.h $(FLAGS_H) \ - function.h hard-reg-set.h $(RESOURCE_H) $(TM_P_H) toplev.h reload.h + function.h hard-reg-set.h $(RESOURCE_H) $(TM_P_H) toplev.h reload.h \ + $(REGS_H) GTFILES = $(srcdir)/input.h $(srcdir)/coretypes.h \ $(CPP_ID_DATA_H) $(host_xm_file_list) \ diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 593b0cbc4939..813dfcf85fba 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -1445,6 +1445,11 @@ enum reg_class #define INDEX_REG_CLASS INDEX_REGS #define BASE_REG_CLASS GENERAL_REGS +/* Unused letters: + B TU W + h jk vw z +*/ + /* Get reg_class from a letter such as appears in the machine description. */ #define REG_CLASS_FROM_LETTER(C) \ @@ -1470,7 +1475,9 @@ enum reg_class (C) == 'y' ? TARGET_MMX ? MMX_REGS : NO_REGS : \ (C) == 'A' ? AD_REGS : \ (C) == 'D' ? DIREG : \ - (C) == 'S' ? SIREG : NO_REGS) + (C) == 'S' ? SIREG : \ + (C) == 'l' ? INDEX_REGS : \ + NO_REGS) /* The letters I, J, K, L and M in a register constraint string can be used to stand for particular ranges of immediate operands. diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index f2c3c44dc591..6ce6ffd3e950 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -5077,7 +5077,7 @@ (define_insn_and_split "*lea_general_1" [(set (match_operand 0 "register_operand" "=r") - (plus (plus (match_operand 1 "index_register_operand" "r") + (plus (plus (match_operand 1 "index_register_operand" "l") (match_operand 2 "register_operand" "r")) (match_operand 3 "immediate_operand" "i")))] "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode @@ -5109,7 +5109,7 @@ (define_insn_and_split "*lea_general_1_zext" [(set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI - (plus:SI (plus:SI (match_operand:SI 1 "index_register_operand" "r") + (plus:SI (plus:SI (match_operand:SI 1 "index_register_operand" "l") (match_operand:SI 2 "register_operand" "r")) (match_operand:SI 3 "immediate_operand" "i"))))] "TARGET_64BIT" @@ -5129,7 +5129,7 @@ (define_insn_and_split "*lea_general_2" [(set (match_operand 0 "register_operand" "=r") - (plus (mult (match_operand 1 "index_register_operand" "r") + (plus (mult (match_operand 1 "index_register_operand" "l") (match_operand 2 "const248_operand" "i")) (match_operand 3 "nonmemory_operand" "ri")))] "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode @@ -5159,7 +5159,7 @@ (define_insn_and_split "*lea_general_2_zext" [(set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI - (plus:SI (mult:SI (match_operand:SI 1 "index_register_operand" "r") + (plus:SI (mult:SI (match_operand:SI 1 "index_register_operand" "l") (match_operand:SI 2 "const248_operand" "n")) (match_operand:SI 3 "nonmemory_operand" "ri"))))] "TARGET_64BIT" @@ -5178,7 +5178,7 @@ (define_insn_and_split "*lea_general_3" [(set (match_operand 0 "register_operand" "=r") - (plus (plus (mult (match_operand 1 "index_register_operand" "r") + (plus (plus (mult (match_operand 1 "index_register_operand" "l") (match_operand 2 "const248_operand" "i")) (match_operand 3 "register_operand" "r")) (match_operand 4 "immediate_operand" "i")))] @@ -5212,8 +5212,9 @@ (define_insn_and_split "*lea_general_3_zext" [(set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI - (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "index_register_operand" "r") - (match_operand:SI 2 "const248_operand" "n")) + (plus:SI (plus:SI (mult:SI + (match_operand:SI 1 "index_register_operand" "l") + (match_operand:SI 2 "const248_operand" "n")) (match_operand:SI 3 "register_operand" "r")) (match_operand:SI 4 "immediate_operand" "i"))))] "TARGET_64BIT" @@ -5235,7 +5236,7 @@ (define_insn "*adddi_1_rex64" [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r") (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,r") - (match_operand:DI 2 "x86_64_general_operand" "rme,re,re"))) + (match_operand:DI 2 "x86_64_general_operand" "rme,re,le"))) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)" { @@ -5503,7 +5504,7 @@ (define_insn "*addsi_1" [(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm,r") (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,r") - (match_operand:SI 2 "general_operand" "rmni,rni,rni"))) + (match_operand:SI 2 "general_operand" "rmni,rni,lni"))) (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (PLUS, SImode, operands)" { @@ -5588,7 +5589,7 @@ [(set (match_operand:DI 0 "register_operand" "=r,r") (zero_extend:DI (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,r") - (match_operand:SI 2 "general_operand" "rmni,rni")))) + (match_operand:SI 2 "general_operand" "rmni,lni")))) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)" { @@ -5937,7 +5938,7 @@ (define_insn "*addhi_1_lea" [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r") (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,r") - (match_operand:HI 2 "general_operand" "ri,rm,rni"))) + (match_operand:HI 2 "general_operand" "ri,rm,lni"))) (clobber (reg:CC FLAGS_REG))] "!TARGET_PARTIAL_REG_STALL && ix86_binary_operator_ok (PLUS, HImode, operands)" @@ -6179,7 +6180,7 @@ (define_insn "*addqi_1_lea" [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r,r") (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,r") - (match_operand:QI 2 "general_operand" "qn,qmn,rn,rn"))) + (match_operand:QI 2 "general_operand" "qn,qmn,rn,ln"))) (clobber (reg:CC FLAGS_REG))] "!TARGET_PARTIAL_REG_STALL && ix86_binary_operator_ok (PLUS, QImode, operands)" @@ -10581,7 +10582,7 @@ (define_insn "*ashldi3_1_rex64" [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r") - (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0,r") + (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0,l") (match_operand:QI 2 "nonmemory_operand" "cJ,M"))) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, DImode, operands)" @@ -10628,7 +10629,7 @@ ;; Convert lea to the lea pattern to avoid flags dependency. (define_split [(set (match_operand:DI 0 "register_operand" "") - (ashift:DI (match_operand:DI 1 "register_operand" "") + (ashift:DI (match_operand:DI 1 "index_register_operand" "") (match_operand:QI 2 "immediate_operand" ""))) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && reload_completed @@ -10782,7 +10783,7 @@ (define_insn "*ashlsi3_1" [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r") - (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0,r") + (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0,l") (match_operand:QI 2 "nonmemory_operand" "cI,M"))) (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (ASHIFT, SImode, operands)" @@ -10828,13 +10829,19 @@ (match_operand:QI 2 "const_int_operand" ""))) (clobber (reg:CC FLAGS_REG))] "reload_completed - && true_regnum (operands[0]) != true_regnum (operands[1])" + && true_regnum (operands[0]) != true_regnum (operands[1]) + && GET_MODE_SIZE (GET_MODE (operands[0])) <= 4" [(const_int 0)] { rtx pat; - operands[0] = gen_lowpart (SImode, operands[0]); - operands[1] = gen_lowpart (Pmode, operands[1]); + enum machine_mode mode = GET_MODE (operands[0]); + + if (GET_MODE_SIZE (mode) < 4) + operands[0] = gen_lowpart (SImode, operands[0]); + if (mode != Pmode) + operands[1] = gen_lowpart (Pmode, operands[1]); operands[2] = gen_int_mode (1 << INTVAL (operands[2]), Pmode); + pat = gen_rtx_MULT (Pmode, operands[1], operands[2]); if (Pmode != SImode) pat = gen_rtx_SUBREG (SImode, pat, 0); @@ -10864,7 +10871,7 @@ (define_insn "*ashlsi3_1_zext" [(set (match_operand:DI 0 "register_operand" "=r,r") - (zero_extend:DI (ashift:SI (match_operand:SI 1 "register_operand" "0,r") + (zero_extend:DI (ashift:SI (match_operand:SI 1 "register_operand" "0,l") (match_operand:QI 2 "nonmemory_operand" "cI,M")))) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, SImode, operands)" @@ -11004,7 +11011,7 @@ (define_insn "*ashlhi3_1_lea" [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r") - (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0,r") + (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0,l") (match_operand:QI 2 "nonmemory_operand" "cI,M"))) (clobber (reg:CC FLAGS_REG))] "!TARGET_PARTIAL_REG_STALL @@ -11129,7 +11136,7 @@ (define_insn "*ashlqi3_1_lea" [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r,r") - (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,r") + (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,l") (match_operand:QI 2 "nonmemory_operand" "cI,cI,M"))) (clobber (reg:CC FLAGS_REG))] "!TARGET_PARTIAL_REG_STALL diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md index a3721a5abe70..3a8eee2152c5 100644 --- a/gcc/config/i386/predicates.md +++ b/gcc/config/i386/predicates.md @@ -474,11 +474,10 @@ { if (GET_CODE (op) == SUBREG) op = SUBREG_REG (op); - return !(op == stack_pointer_rtx - || op == arg_pointer_rtx - || op == frame_pointer_rtx - || (REGNO (op) >= FIRST_PSEUDO_REGISTER - && REGNO (op) <= LAST_VIRTUAL_REGISTER)); + if (reload_in_progress || reload_completed) + return REG_OK_FOR_INDEX_STRICT_P (op); + else + return REG_OK_FOR_INDEX_NONSTRICT_P (op); }) ;; Return false if this is any eliminable register. Otherwise general_operand. diff --git a/gcc/genpreds.c b/gcc/genpreds.c index 1eebc331c303..874925de998b 100644 --- a/gcc/genpreds.c +++ b/gcc/genpreds.c @@ -437,7 +437,8 @@ write_insn_preds_c (void) #include \"hard-reg-set.h\"\n\ #include \"resource.h\"\n\ #include \"toplev.h\"\n\ -#include \"reload.h\"\n"); +#include \"reload.h\"\n\ +#include \"regs.h\"\n"); FOR_ALL_PREDICATES (p) write_one_predicate_function (p); -- 2.43.5